AK4125_07 Datasheet, PDF (21/26 Pages) Asahi Kasei Microsystems – 192kHz / 24Bit High Performance Asynchronous SRC

• Input PORT: Slave Mode, IBICK lock mode (64fsi), 24bit MSB justified
• Output PORT: Master mode, 24bit MSB justified
• Dither = OFF
[AK4125]
0.22μ
470 _1.0n
1 FILT
2 AVSS
10μ
AVDD 30 _0.1μ
DVSS 29
Reset
fsi
64fsi
3 PDN
4 SMUTE
5 DITHER
6 PLL2
7 ILRCK
AK4125
DVDD 28
0.1μ
OMCLK 27
128fso
fso
OLRCK 26
OBICK 25
64fso
SDTO 24
8 IBICK
ODIF1 23
DSP, uP
9 SDTI
10 IDIF0
ODIF0 22
CMODE2 21
11 IDIF1
CMODE1 20
12 IDIF2
CMODE0 19
13 PLL0
IMCLK 18
14 PLL1
OBIT1 17
15 UNLOCK
OBIT0 16
Supply
3.0 ~ 3.6V
DSP
Note:
- AVSS and DVSS of the AK4125 should be distributed separately from the ground of external digital
devices (MPU, DSP etc.).
- All digital input pins should not be left floating.
Figure 16. Typical Connection Diagram (Master mode)
1. Grounding and Power Supply Decoupling
The AK4125 requires careful attention to power supply and grounding arrangements. Alternatively if AVDD and DVDD
are supplied separately, the power up sequence is not important. Decoupling capacitors should be as near to the AK4125 as
possible, with the small value ceramic capacitor being the nearest.
MS0379-E-04
- 21 -
2007/07