AK4125_07 Datasheet, PDF (17/26 Pages) Asahi Kasei Microsystems – 192kHz / 24Bit High Performance Asynchronous SRC

[AK4125]
■ Dither
The AK4125 has a dither circuit. The dither circuit adds the dither to the LSB of the output data, which is the value of the
OBIT1-0 pins, by DITHER pin = “H” regardless of the SRC mode or the SRC bypass mode.
■ System Reset
Bringing the PDN pin = “L” sets the AK4125 power-down mode and initializes the digital filter. The AK4125 should be
reset once by bringing the PDN pin = “L” when power-up. When the PDN pin = “L”, the SDTO output is “L”. The SDTO
valid time is 100ms. Until the output data becomes valid, the SDTO pin outputs “L”.
Case 1
External clocks
(Input port) ^{Don’t care}
SDTI
Don’t care
External clocks
(Output port)
Don’t care
Input Clocks 1
Input Data 1
Output Clocks 1
Input Clocks 2
Input Data 2
Output Clocks 2
Don’t care
Don’t care
Don’t care
PDN
(Internal state) Power-down
< 100ms
PLL lock &
fs detection
Normal
operation
< 100ms
PD
PLL lock &
fs detection
Normal
operation
Power-down
SDTO
“0” data
Normal data
“0” data
Normal data “0” data
UNLOCK
Case 2
External clocks
(Input port)
SDTI
External clocks
(Output port)
PDN
(Internal state) Power-down
Figure 11. System Reset
(No Clock)
(Don’t care)
(Don’t care)
Input Clocks
Input Data
Output Clocks
Don’t care
Don’t care
Don’t care
PLL Unlock
< 100ms
PLL lock &
fs detection
Normal
operation
Power-down
SDTO
“0” data
Normal data “0” data
UNLOCK
Figure 12. System Reset 2
MS0379-E-04
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2007/07