AKD4753-A Datasheet, PDF (8/60 Pages) Asahi Kasei Microsystems – AK4753 Evaluation Board Rev.2

■ DIR SW Setting
Upper-side is “ON(H)” and lower-side is “OFF(L)”.
[S3] (SW DIP-4): Mode setting for AK4118A.
No.
Name
ON (“H”)
OFF (“L”)
1
OCKS0
AK4118A Master Clock Setting
2
OCKS1
See Table 3
3
DIF0
AK4118A Audio Interface Format Setting
4
DIF1
See Table 4
Table 2. Mode Setting for AK4118A
[AKD4753-A]
Default
OFF
OFF
ON
OFF
OCKS1
L
H
H
OCKS0
L
L
H
MCKO1
256fs
512fs
Not to use
Default
Table 3. Setting for AK4118A Master Clock Setting
DIF2
Fixed
”H”
DIF1
L
L
H
H
DIF0
L
H
L
H
SDTO
24bit, Left justified
24bit, I²S
24bit, Left justified
24bit, I²S
LRCK
H/L O
L/H O
H/L I
L/H I
BICK
64fs O
64fs O
64-128fs I
64-128fs I
Default
Table 4. Setting for AK4118A Audio Interface Format Setting
[S4] (SW DIP-2): Mode setting for AK4753.
No.
Name
ON (“H”)
OFF (“L”)
Default
1
EXTEE EEP-ROM Download Mode Serial Control Mode OFF
2 BYPASS
DSP Bypass Mode
Normal Operation
OFF
Table 5. Mode Setting for AK4753
KM103902
-8-
2011/01