AKD4753-A Datasheet, PDF (5/60 Pages) Asahi Kasei Microsystems – AK4753 Evaluation Board Rev.2

[AKD4753-A]
4) PLL Master Mode
(a) All interface signals including master clock are fed externally.
(a-1) Setup the MCKI.
X1(X’Tal) or J7(MCKI) are used. Nothing should be connected to PORT1(RX).
(a) When using X1(X’Tal)
JP3
JP7
AK4753-MCLK
(b) When using J7(MCKI)
JP3
JP7
AK4753-MCLK
Figure 7. Setup the MCKI
(a-2) Other Setting (BICK, LRCK and SDATA).
PORT3(DSP) is used. Nothing should be connected to PORT1(RX).
JP4
JP5
JP6
AK4753-BICK _{AK4753-SDATA AK4753-LRCK}
DIR EXT
DIR EXT DIR EXT
JP17
MODE_SEL
JP18
MCLK_SEL
MASTER SLAVE MUTEN MCLK
Figure 8. Other Setting (BICK, LRCK and SDATA)
KM103902
-5-
2011/01