AKD4753-A Datasheet, PDF (4/60 Pages) Asahi Kasei Microsystems – AK4753 Evaluation Board Rev.2

[AKD4753-A]
2) External Master Mode
(a) Evaluation of D/A using DIR of AK4118A.
In case of AK4753 evaluation using AK4118A, it is necessary to correspond to audio interface format for
AK4753 and AK4118A.Please use AK4118A in the slave mode.
PORT1(RX) is used. Nothing should be connected to PORT3(DSP) and J7(MCKI).
JP3
JP4
JP5
JP6
JP7
AK4753-BICK AK4753-SDATA AK4753-LRCK AK4753-MCLK
DIR EXT
DIR EXT DIR EXT
Figure 4. Setting of D/A using DIR of AK4118A
3) PLL Slave Mode
(a) Evaluation of D/A using DIR of AK4118A.
In case of AK4753 evaluation using AK4118A, it is necessary to correspond to audio interface format for
AK4753 and AK4118A.Please use AK4118A in the master mode.
PORT1(RX) is used. Nothing should be connected to PORT3(DSP) and J7(MCKI).
JP3
JP4
JP5
JP6
JP7
AK4753-BICK _{AK4753-SDATA AK4753-LRCK AK4753-MCLK}
DIR EXT
DIR EXT DIR EXT
Figure 5. Setting of D/A using DIR of AK4118A
(b) All interface signals including master clock are fed externally.
PORT3(DSP) is used. Nothing should be connected to PORT1(RX) and J7(MCKI).
JP3
JP4
JP5
JP6
JP7
AK4753-BICK _{AK4753-SDATA AK4753-LRCK AK4753-MCLK}
DIR EXT
DIR EXT DIR EXT
JP17
MODE_SEL
JP18
MCLK_SEL
KM103902
MASTER SLAVE MUTEN MCLK
Figure 6. Setting of all interface signals including master clock are fed externally
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2011/01