AKD4121A_07 Datasheet, PDF (8/36 Pages) Asahi Kasei Microsystems – Asynchronous Sample Rate Converter

ASAHI KASEI
[AKD4121A]
No.
X’tal / External clock
(Max: 24.576MHz)
DIP SW3 setting
DIR-CM0
OCKS0
SW3-4
SW3-5
1
256fs
ON
1/2 MCLK
2
512fs
ON
MCLK
Table 5. DIR(AK4112B)’s clock setting(Refer following figures)
12345
12345
fsi-DIR 1/2MCLK
SW3
MCLK:256fsi
fsi-DIR 1/2MCLK
SW3
MCLK:512fsi
Figure 7. DIP SW(SW3) setting(Refer following figures)
1-3-b Audio Interface Format setting
Refer “1-2-b Refer Audio Interface Format setting”
<KM088800>
-8-
2007/03