AKD4121A_07 Datasheet, PDF (11/36 Pages) Asahi Kasei Microsystems – Asynchronous Sample Rate Converter

ASAHI KASEI
[AKD4121A]
2-2. Clocks are fed through the 10-pin port(PORT3)
2-2-1. AK4121A in Master Mode
2-2-1-a. Jumper setting
Parts No.
Setting
JP5
PORT3
JP6
OPEN
JP8
OPEN
JP9
OPEN
JP7
OPEN
JP11
OPEN
Table 8. Jumper setting(Refer following figures)
JP5
DIT
JP6
JP8
JP9
JP7
PORT3
JP11
PORT3
DIR
SRC-MCLK DIT-SOURCE
OBICK OLRCK
Using X’tal on-board
Figure 10. Jumper setting
SDTO
10pin
Bypass
Output
2-2-1-b. Audio Interface Format
Mod SW4-1 SW4-2 SW4-3
e CMODE2 CMODE1 CMODE0
MCLK
Master/Slave (Output Port)
0
L
L
L
256fso (fso~96kHz)
Master
1
L
L
H
384fso (fso~96kHz)
Master
2
L
H
L
512fso (fso~48kHz)
Master
3
L
H
H
768fso (fso~48kHz)
Master
Table 9. AK4121A System Clock setting
<KM088800>
- 11 -
2007/03