AKD4121A_07 Datasheet, PDF (15/36 Pages) Asahi Kasei Microsystems – Asynchronous Sample Rate Converter

ASAHI KASEI
[AKD4121A]
3. Bypass Mode
In case of Bypass Mode, please set DIP switch (SW3) as follows.
Mod SW4-1 SW4-2
SW4-3
e CMODE2 CMODE1 CMODE0
MCLK
Master/Slave (Output Port)
7
H
H
H
Not used. Set to DVSS
Master(Bypass)
Table 14. AK4121A System Clock setting
12345
CMODE
SW4
Figure 13. DIP switch setting
3-1. Setting of input block
3-1-1. Optical Input(PORT2)
3-1-1-a. Jumper setting
Parts No.
Setting
JP1
OUT
JP2
SHORT
JP3
SHORT
JP4
SHORT
X1
(don’t care)
Table 15. Jumper setting(Refer following figures)
JP1
JP2
JP3
JP4
OUT
IN
IMCLK
IBICK
SDTI
ILRCK
Figure 14. Jumper setting
3-1-1-b. Audio Interface Format setting (IIS only)
12345
fsi-DIR 1/2MCLK
SW3
Figure 15. DIP switch (SW3) setting
<KM088800>
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2007/03