AKD4121A_07 Datasheet, PDF (5/36 Pages) Asahi Kasei Microsystems – Asynchronous Sample Rate Converter

ASAHI KASEI
[AKD4121A]
1-2. All clock are fed through the 10-pin port
1-2-a. Jumper setting
Parts No.
Setting
JP1
(don’t care)
JP2
OPEN
JP3
OPEN
JP4
OPEN
SW3-4
(don’t care)
X1
(don’t care)
Table 2. Jumper Setting (Refer following figures)
JP1
JP2
JP3
JP4
OUT
IN
IMCLK
IBICK
SDTI
ILRCK
Figure 4. Jumper Setting
1-2-b. Audio Interface Format setting
Audio Interface
Format
SW3-1
DIF2
SRC:AK4121A
SW3-2
DIF1
SW3-3
DIF0
16bit, Right justified
0
0
0
20bit, Right justified
0
0
1
Left justified
0
1
0
I²S
0
1
1
24bit, Right justified
1
0
0
Table 3. DIP switch (SW3) setting(Refer following figures)
12345
fsi-DIR 1/2MCLK
SW3
16bit, Right justified
12345
fsi-DIR 1/2MCLK
SW3
20bit, Right justified
<KM088800>
-5-
2007/03