AKD4121A_07 Datasheet, PDF (22/36 Pages) Asahi Kasei Microsystems – Asynchronous Sample Rate Converter

ASAHI KASEI
[AKD4121A]
„ DIP switch list
SW3(fsi-DIR)
No. Switch Name
1, 2, 3 IDIF2, 1, 0
4
DIR-CM0
5
MCLK
1/2MCLK
Default
OFF, ON, ON (IIS)
OFF (Optical)
MCLK
Function
fsi data format. Refer Table 3.
DIR clock mode.
ON : X’tal mode
OFF : Optical mode
DIR MCLK select.
MCLK : 512fs
1/2MCLK : 256fs
SW4(CMODE)
No. Switch Name
1, 2, 3 CMODE2, 1, 0
4, 5 DEM1, 0
Default
OFF, ON, OFF
(Master, 512fso)
OFF, ON (off)
Function
System clock selects. Refer Table 9, Table 12 and Table 14
De-emphasis control. Refer Table 12.
SW5(fso)
No. Switch Name
1,2 ODIF1, 0
3
MCLK
1/2MCLK
Default
ON, ON (IIS)
MCLK
„ Toggle switch list (SW1 and SW2)
Function
fso data format. Refer Table 10.
DIT MCLK select.
MCLK : 512fs
1/2MCLK : 256fs
SW1 is reset switch for AK4121A, AK4112B(DIR) and AK4114(DIT). Set to “H” during Normal operation.
Bring to “L” once after the power is supplied.
SW2 is SMUTE control switch. Refer Table 23.
„ LED
Bright when ERF pin of AK4112B goes to “H”.
This indicates the UNLOCK state, etc. (Refer AK4112B datasheet).
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2007/03