AKD4121A_07 Datasheet, PDF (18/36 Pages) Asahi Kasei Microsystems – Asynchronous Sample Rate Converter

ASAHI KASEI
[AKD4121A]
3-2. Setting of output block
3-2-1. Optical Output(PORT4). Clock are fed from AK4114 (DIT). (IIS Master Mode only.)
3-2-1-a. Jumper setting
Parts No.
JP8
JP9
JP7
JP5
JP6
JP11
X2
Setting
SHORT
SHORT
SHORT
(don’t care)
DIR
OPEN
Remove
Table 18. Jumper setting
JP5
DIT
JP6
JP8
JP9
JP7
JP11
PORT3
PORT3
DIR
SRC-MCLK DIT-SOURCE
(don’t care)
OBICK OLRCK
Figure 18. Jumper setting
No.
X1or External Clock (PORT1)
(Max: 24.576MHz)
DIP SW3 setting
OCKS0
SW3-5
1
256fs
1/2 MCLK
2
512fs
MCLK
Table 19. DIR/DIT Clock setting
ILRCK
10pin
Bypass
Output
DIP SW5 setting
OCKS0
SW5-3
1/2 MCLK
MCLK
123
123
fso 1/2 MCLK
SW5
MCLK:256fso
fso 1/2 MCLK
SW5
MCLK:512fso
Figure 19. DIP switch setting
<KM088800>
- 18 -
2007/03