AK4589_1 Datasheet, PDF (72/76 Pages) Asahi Kasei Microsystems – 2/8-Channel Audio CODEC with DIR

ASAHI KASEI
[AK4589]
SYSTEM DESIGN
Figure 50 shows the system connection diagram. An evaluation board is available which demonstrates application
circuits, the optimum layout, power supply arrangements and measurement results.
Condition: I²C serial control mode
Audio DSP
(MPEG/AC3)
Micro
Controller
S/PDIF out
S/PDIF sources
5
(S/PDIF
sources)
10u
+
0.1u
3.3V to 5V
Digital
Digital 5V
Micro
Controller
10u
C1
C1
1 INT1
2 BOUT
0.1u
+
3 TVDD
4 DVDD
+
5 DVSS
6 XTO
X’tal
7 XTI
8 TEST3
9 MCKO2
10 MCKO1
11 COUT
12 UOUT
13 VOUT
14 SDTO2
15 BICK2
16 LRCK2
17 SDTO1
18 BICK1
19 LRCK1
20 CDTO
AK4589
TEST1 ₆₀
RX1 59
NC 58 (Shield)
RX0 57
AVSS ₅₆
AVDD ₅₅
VREFH 54
VCOM ₅₃
RIN ₅₂
+
0.1u 10u _{Analog 5V}
0.1u 2.2u
+
LIN 51
ROUT1+ 50
ROUT1- 49
LOUT1+ ₄₈
LOUT1- 47
ROUT2+ 46
ROUT2- ₄₅
LOUT2+ 44
LOUT2- 43
ROUT3+ ₄₂
ROUT3- 41
C2
LPF
C2
LPF
C2
LPF
C2
LPF
C2
LPF
MUTE
MUTE
MUTE
MUTE
MUTE
C2
C2
C2
LPF LPF LPF
Audio DSP
(MPEG/AC3)
Micro Controller
Digital Ground
Analog Ground
Figure 50. Typical Connection Diagram
Notes:
- “C1” depends on the crystal.
- “C2” is 470pF capacitor.
- AVSS, DVSS and PVSS must be connected the same analog ground plane.
- Digital signals, especially clocks, should be kept away from the R pin in order to avoid an effect to the clock jitter
performance.
- In case of coaxial input, ground of RCA connector and terminator should be connected to PVSS of the AK4589
with low impedance on PC board.
MS0339-E-00
- 72 -
2004/09