AK4589_1 Datasheet, PDF (25/76 Pages) Asahi Kasei Microsystems – 2/8-Channel Audio CODEC with DIR

ASAHI KASEI
[AK4589]
OPERATION OVERVIEW (ADC/DAC part)
System Clock
The external clocks, which are required to operate the AK4589, are MCLK, LRCK1 and BICK1. MCLK should be
synchronized with LRCK1 but the phase is not critical. There are two methods to set MCLK frequency. In Manual
Setting Mode (ACKS bit = “0”: Default), the sampling speed is set by DFS1-0 bit (Table 1). The frequency of MCLK at
each sampling speed is set automatically. (Table 3, 4, 5) In Auto Setting Mode (ACKS bit = “1”), as MCLK frequency
is detected automatically (Table 6) and the internal master clock becomes the appropriate frequency (Table 7), it is not
necessary to set DFS1-0 bits.
Only MCLK is necessary in the master mode. Master Clock Input Frequency should be selected by CKS1-0 bits (Table
2), and Sampling Speed should be selected by DFS1-0 bits (Table 1). The frequencies and the duties of the clocks
(LRCK1, BICK1) may not be stabile after setting CKS1-0 bits and DFS1-0 bits up.
In slave mode, external clocks (MCLK, BICK1, LRCK1) should always be present whenever the AK4589 is in normal
operation mode (PDN pin = “H”). If these clocks are not provided, the AK4589 may draw excess current because the
device utilizes dynamic refreshed logic internally. If the external clocks are not present, the AK4589 should be in the
power-down mode (PDN pin = “L”) or in the reset mode (RSTN1 bit = “0”). After exiting reset at power-up etc., the
AK4589 is in the power-down mode until MCLK and LRCK are input.
In the Master mode, External clock(MCLK) should always be supplied except in the power-down mode. It is in
power-down mode until MCLK will be supplied, when Reset was canceled by Power-ON and so on.
DFS1
0
0
1
DFS0
0
1
0
Sampling Speed (fs)
Normal Speed Mode
32kHz~48kHz
Double Speed Mode
64kHz~96kHz
Quad Speed Mode
120kHz~192kHz
Default
Table 1. Sampling Speed (Manual Setting Mode)
CKS1
0
0
1
1
CKS0
0
1
0
1
Normal
256fs
384fs
512fs
256fs
Double
128fs
192fs
256fs
256fs
Quad
128fs
128fs
128fs
128fs
Default
Table 2.Master clock input select (Master Mode)
LRCK1
Fs
32.0kHz
44.1kHz
48.0kHz
256fs
8.1920
11.2896
12.2880
MCLK (MHz)
384fs
12.2880
16.9344
18.4320
512fs
16.3840
22.5792
24.5760
BICK1 (MHz)
64fs
2.0480
2.8224
3.0720
Table 3. System Clock Example (Normal Speed Mode @Manual Setting Mode)
LRCK1
Fs
88.2kHz
96.0kHz
128fs
11.2896
12.2880
MCLK (MHz)
192fs
16.9344
18.4320
256fs
22.5792
24.5760
BICK1 (MHz)
64fs
5.6448
6.1440
Table 4. System Clock Example (Double Speed Mode @Manual Setting Mode)
(Note: At Double speed mode (DFS1= “0”, DFS0 = “1”), 128fs and 192fs are not available for ADC.)
MS0339-E-00
- 25 -
2004/09