AK4589_1 Datasheet, PDF (51/76 Pages) Asahi Kasei Microsystems – 2/8-Channel Audio CODEC with DIR

ASAHI KASEI
[AK4589]
Error Handling
There are the following eight events that make INT0/1 pins “H”. INT0/1 pins show the status of following conditions.
1. UNLOCK: “1” when the PLL loses lock.
The AK4589 loses lock when the distance between two preambles is not correct or when those
preambles are not correct.
2. PAR:
“1” when parity error or biphase coding error is detected, and keeps “1” until this register is read.
Updated every sub-frame cycle. Reading this register resets itself.
3. AUTO:
“1” when Non-PCM bitstream is detected.
Updated every 4096 frames cycle.
4. DTSCD: “1” when DTS-CD bitstream is detected.
Updated every DTS-CD sync cycle.
5. AUDION: “1” when the “AUDIO” bit in recovered channel status indicates “1”.
Updated every block cycle.
6. PEM:
“1” when “PEM” in recovered channel status indicates “1”.
Updated every block cycle.
7. QINT:
“1” when Q-subcode differ from old one, and keeps “1” until this register is read.
Updated every sync code cycle for Q-subcode. Reading this register resets itself.
8. CINT:
“1” when received C bits differ from old one, and keeps “1” until this register is read.
Updated every block cycle. Reading this register resets itself.
Both INT0/1 are fixed to “L” when the PLL is off (CM1,0= “01”). Once the INT0 pin goes to “H”, this pin holds “H” for
1024/fs cycles (this value can be changed by EFH0/1 bits) after those events are removed. INT1 pin goes to “L” at the
same time when those events are removed. Each INT0/1 pins can mask those eight events individually. Once PAR, QINT
and CINT bit goes to “1”, those registers are held to “1” until those registers are read. While the AK4589 loses lock,
registers regarding C-bit or U-bits are not initialized and keep previous value.
INT0/1 pin output the ORed signal among those eight events. However, each events can be masked by each mask bits.
When each bit masks those events, the event does not affect INT0/1 pins operation (those mask do not affect those
registers (UNLOCK, PAR, etc.) themselves. Once INT0 pin goes “H”, it maintains “H” for 1024/fs cycles (this value can
be changed by EFH0-1 bits) after the all events are removed. Once those PAR, QINT or CINT bit goes “1”, it holds “1”
until reading those registers. While the AK4589 loses lock, the channel status an Q-subcode bits are not updated and
holds the previous data. At initial state, INT0 outputs the ORed signal between UNLOCK and PAR, INT1 outputs the
ORed signal among AUTO, DTSCD and AUDION.
Register
Pin
UNLOCK PAR AUTO DTSCD AUDION PEM QINT CINT SDTO2
V
TX
1
x
x
x
x
x
x
x
“L”
“L” Output
0
1
x
x
x
x
x
x Previous Data Output Output
0
0
1
x
x
x
x
x
Output
Output Output
0
0
x
1
x
x
x
x
Output
Output Output
0
0
x
x
1
x
x
x
Output
Output Output
0
0
x
x
x
1
x
x
Output
Output Output
0
0
x
x
x
x
1
x
Output
Output Output
0
0
x
x
x
x
x
1
Output
Output Output
Table 28. Error Handling
MS0339-E-00
- 51 -
2004/09