AK4589_1 Datasheet, PDF (67/76 Pages) Asahi Kasei Microsystems – 2/8-Channel Audio CODEC with DIR

ASAHI KASEI
[AK4589]
OPERATION OVERVIEW (ADC/DAC part, DIR/DIT part)
Serial Control Interface
The AK4589 has two registers, which are ADC/DAC part (AK4588 compatible) and DIR/DIT part (AK4588
compatible). Each register is set by chip address pin.
(1) 4-wire serial control mode (I2C pin = “L”)
The internal registers may be either written or read by the 4-wire µP interface pins: CSN, CCLK, CDTI & CDTO. The
data on this interface consists of Chip address (2bits, ADC/DAC part register is set by CAD1/0 pins. DIR/DIT part C1-0
bits are fixed to “00”), Read/Write (1bit), Register address (MSB first, 5bits) and Control data (MSB first, 8bits).
Address and data is clocked in on the rising edge of CCLK and data is clocked out on the falling edge. For write
operations, data is latched after the 16th rising edge of CCLK, after a high-to-low transition of CSN. For read
operations, the CDTO output goes high impedance after a low-to-high transition of CSN. The maximum speed of
CCLK is 5MHz. PDN pin = “L” resets the registers to their default values. When the state of P/S pin is changed, the
AK4589 should be reset by PDN pin = “L”. Register of ADC/DAC part can not read.
CSN
CCLK
WRITE
CDTI
CDTO
READ
CDTI
CDTO
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
C1 C0 R/W A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
Hi-Z
C1 C0 R/W A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
Hi-Z
Hi-Z
D7 D6 D5 D4 D3 D2 D1 D0
C1-C0: Chip Address: (Regarding ADC/DAC part, register is set by CAD1/0
pins. This chip address must be set except “00”.)
(Fixed to “00” for DIR/DIT part)
R/W: READ/WRITE (0:READ, 1:WRITE)
A4-A0: Register Address
D7-D0: Control Data
Figure 40. 4-wire Serial Control I/F Timing
MS0339-E-00
- 67 -
2004/09