AK4589_1 Datasheet, PDF (40/76 Pages) Asahi Kasei Microsystems – 2/8-Channel Audio CODEC with DIR

ASAHI KASEI
[AK4589]
Addr Register Name
01H Control 2
Default
D7 D6
D5
D4
D3
CKS1 DFS1 LOOP1 LOOP0 SDOS
0
0
0
0
0
D2
DFS0
0
D1
ACKS
0
D0
CKS0
0
ACKS: Master Clock Frequency Auto Setting Mode Enable
0: Disable, Manual Setting Mode
1: Enable, Auto Setting Mode
Master clock frequency is detected automatically at ACKS bit “1”. In this case, the setting of DFS1-0
bits are ignored. When this bit is “0”, DFS1-0 bits set the sampling speed mode.
DFS1-0: Sampling speed mode (see Table 1)
The setting of DFS1-0 bits are ignored at ACKS bit “1”.
CKS0-1: Master clock frequency select (see Table 2)
SDOS: SDTO1 source select
0: ADC
1: DAUX
SDOS bit should be set to “0” at TDM bit “1”.
In the case of PWADN bit =”0” and PWDAN bit =”0”, the setting of SDOS bit becomes invalid. And
ADC is selected.
The output of SDTO1 becomes “L” at PWADN bit =”0”.
LOOP1-0: Loopback mode enable
00: Normal (No loop back)
01: LIN → LOUT1, LOUT2, LOUT3, LOUT4
RIN → ROUT1, ROUT2, ROUT3, ROUT4
The digital ADC output (DAUX1 input if SDOS = “1”) is connected to the digital DAC input. In
this mode, the input DAC data to SDTI1-3 is ignored. The audio format of SDTO1 at loopback
mode becomes mode 2 at mode 0, and mode 3 at mode 1, respectively.
10: SDTI1(L) → SDTI2(L), SDTI3(L), SDTI4(L)
SDTI1(R) → SDTI2(R), SDTI3(R), SDTI4(R)
In this mode the input DAC data to SDTI2-4 is ignored.
11: N/A
LOOP1-0 bits should be set to “00” at TDM bit “1”.
In the case of PWADN bit =”0” and PWDAN bit =”0”, the setting of LOOP1-0 bits become
invalid. And ADC is selected. And it becomes the normal operation (No loop back).
MS0339-E-00
- 40 -
2004/09