AK4589_1 Datasheet, PDF (15/76 Pages) Asahi Kasei Microsystems – 2/8-Channel Audio CODEC with DIR

ASAHI KASEI
[AK4589]
Parameter
Symbol
min
typ
max
Audio Interface Timing (Slave Mode)
Normal mode
BICK1 Period
tBCK
81
BICK1 Pulse Width Low
tBCKL
32
Pulse Width High
tBCKH
32
LRCK1 Edge to BICK1 “↑” (Note 19)
tLRB
20
BICK1 “↑” to LRCK1 Edge (Note 19)
tBLR
20
LRCK1 to SDTO1(MSB)
tLRS
40
BICK1 “↓” to SDTO1
tBSD
40
SDTI1-4,DAUX1 Hold Time
tSDH
20
SDTI1-4,DAUX1 Setup Time
tSDS
20
TDM 256 mode
BICK1 Period
tBCK
81
BICK1 Pulse Width Low
tBCKL
32
Pulse Width High
tBCKH
32
LRCK1 Edge to BICK1 “↑” (Note 19)
tLRB
20
BICK1 “↑” to LRCK1 Edge (Note 19)
tBLR
20
BICK1 “↓” to SDTO1
tBSD
20
SDTI1 Hold Time
tSDH
10
SDTI1 Setup Time
tSDS
10
TDM 128 mode
BICK1 Period
tBCK
81
BICK1 Pulse Width Low
tBCKL
32
Pulse Width High
tBCKH
32
LRCK1 Edge to BICK1 “↑” (Note 19)
tLRB
20
BICK1 “↑” to LRCK1 Edge (Note 19)
tBLR
20
BICK1 “↓” to SDTO1
tBSD
20
SDTI1-2 Hold Time
tSDH
10
SDTI1-2 Setup Time
tSDS
10
Audio Interface Timing (Master Mode)
Normal mode
BICK1 Frequency
fBCK
64fs
BICK1 Duty
dBCK
50
BICK1 “↓” to LRCK1 Edge
tMBLR
-20
20
BICK1“↓” to SDTO1
tBSD
40
SDTI1-4,DAUX1 Hold Time
tSDH
20
SDTI1-4,DAUX1 setup Time
tSDS
20
TDM 256 mode
BICK1 Frequency
fBCK
256fs
BICK1 Duty
(Note 20)
dBCK
50
BICK1 “↓” to LRCK1 Edge
tMBLR
-12
12
BICK1 “↓” to SDTO1
tBSD
20
SDTI1 Hold Time
tSDH
10
SDTI1 Setup Time
tSDS
10
TDM 128 mode
BICK1 Frequency
fBCK
128fs
BICK1 Duty
(Note 21)
dBCK
50
BICK1 “↓” to LRCK1 Edge
tMBLR
-12
12
BICK1 “↓” to SDTO1
tBSD
20
SDTI1-2 Hold Time
tSDH
10
SDTI1-2 Setup Time
tSDS
10
Notes:
19. BICK1 rising edge must not occur at the same time as LRCK1 edge.
20. When MCLK is 512fs, dBCK is guaranteed. When 384fs and 256fs, dBCK can not be guaranteed.
21. When MCLK is 256fs, dBCK is guaranteed. When 128fs, dBCK can not be guaranteed.
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Hz
%
ns
ns
ns
ns
Hz
%
ns
ns
ns
ns
Hz
%
ns
ns
ns
ns
MS0339-E-00
- 15 -
2004/09