AK8859VQ Datasheet, PDF (53/73 Pages) Asahi Kasei Microsystems – NTSC/PAL/SECAM Digital Video Decoder

[AK8859VQ]
[9.1.6.] Sub Address 0x05 “Output Pin Control Register (R/W)”
Output pins status setting register.
Sub Address: 0x05
bit 7
bit 6
VARSEL1
VARSEL0
Default Value
0
0
bit 5
VD_FSEL
0
bit 4 bit 3
OEN HL
0
1
bit 2
VARL
1
Default Value: 0x0F
bit 1
bit 0
VD_FL
DL
1
1
Output Pin Control Register Definition
Bit ^Register
Name
bit 0 DL
D Output Low
bit 1 VD_FL
VD/FIELD Low
bit 2 VARL
VAR Low
bit 3 HL
bit 4 OEN
bit 5 VD_FSEL
HD Low
Output
Enable
VD/FIELD
Select
bit 6 VARSEL0
~
~
bit 7 VARSEL1
DVALID/FIELD
NSIG/LINE
Select
R/W Definition
[0]: Normal output
R/W _{[1]: [D17: D0] pin output fixed at Low}
[0]: Normal output
R/W _{[1]: VD_F pin output fixed at Low}
[0]: Normal output
R/W
[1]: VAR pin output fixed at Low
R/W ^{[0]: Normal output}
[1]: HD pin output fixed at Low
R/W ^{[0]: Normal output for each digital output pins*}
[1]: Hi-Z output for each digital output pins.
VD_F pin output signal selection.
R/W [0]: VD signal output
[1]: FIELD signal output
VAR pin output signal selection
[ VARSEL1 : VARSEL0 ]
[00]: DVALID signal output from VAR-pin
NSIG signal output from VARSUB-pin
R/W
[01]: FIELD signal output from VAR-pin
LINE signal output from VARSUB-pin
[10]: NSIG signal output from VAR-pin
FIELD signal output from VARSUB-pin
[11]: LINE signal output from VAR-pin
DVALID signal output from VARSUB-pin
*Collective term for DTCLK, DATA[7:0], HD, VD_F, VAR and VARSUB pins.
However, the PDN pin states will have priority regardless of these register setting. When PDN pin is Low
output, the output from the DTCLK, DATA[7:0], VD_F, VAR, VARSUB and HD pins is Low output.
MS1178-E-00
AKM Confidential
- 53 -
2010/04