AK8859VQ Datasheet, PDF (14/73 Pages) Asahi Kasei Microsystems – NTSC/PAL/SECAM Digital Video Decoder

[5.3.] Output data timing
[AK8859VQ]
DTCLK^(*1)
tDS
tDH
0.5PVDD
Output Data^(*2)
0.5PVDD
Parameter
Output Data Setup Time
Output Data Hold Time
Symbol
Min.
Typ.
tDS
10
tDH
10
(*1) It is possible to invert the polarity of DTCLK via register setting.
(*2) Output Data is general term of DATA[7:0], HD, VD_F, VAR and VARSUB.
Max.
Unit
nsec
nsec
[5.4.] Power down sequence
sVREF
PDN
VIL
VIH
VIL
nPDN
aPDN
Parameter
Power down pulse removal period
Power down pulse width
VREF stabilization period
Symbol
Min.
Typ.
Max.
Unit
nPDN
50
nsec
aPDN
500
nsec
sVREF
10
msec
At power down, DTCLK pin, DATA[7:0] pin, HD pin, VD_F pin, VAR pin and VARSUB pin is Low output.
After power down released, DATA[7:0] pin, HD pin, VD_F pin, VAR pin and VARSUB pin is stay Low output
if no register setting apply. Register setting only apply after VREF stabilization period.
MS1178-E-00
AKM Confidential
- 14 -
2010/04