AK8859VQ Datasheet, PDF (33/73 Pages) Asahi Kasei Microsystems – NTSC/PAL/SECAM Digital Video Decoder

[AK8859VQ]
[7.22.2.2.] Fixed-clock mode
In fixed-clock mode, the internal clock is not synchronized with the output signal, but a space of 122/132
(NTSC/PAL) pixels is guaranteed between the horizontal sync signal and the start of the active video
interval.
(For example, composite video signal input timing is shown below and 1pixel = 2CLK)
Video Signal
HD
DVALID
128CLK
····· SAV Cb0 Y0 Cr0 Y1 Cb1 Y2 Cr1 Y3 ······ Y718 Cr359 Y719 FF ··············
244CLK
(264CLK)
1440CLK
Active video interval
32CLK
(24CLK)
Fixed
Not fixed
[7.23] Digital Pixel interpolator
The digital pixel interpolator of the AK8859VQ aligns vertical pixel positions in both frame-lock and
fixed-clock operating modes. The pixel interpolator can be set to ON or OFF via register. With a register
setting of AUTO, the pixel interpolator is OFF or ON depending on the clock mode, as follows.
Line-locked clock mode
Frame-locked clock mode
Fixed-clock mode
OFF
ON
ON
Settings for pixel interpolator operation
Name
Setting Value _{Interpolator operation Notes}
Sub Address: 0x08 [5:4]
[00]
INTPOL0
[01]
~
INTPOL1
[10]
[11]
Auto
ON
OFF
Reserved
Dependent on clock mode.
MS1178-E-00
AKM Confidential
- 33 -
2010/04