AK8859VQ Datasheet, PDF (47/73 Pages) Asahi Kasei Microsystems – NTSC/PAL/SECAM Digital Video Decoder

[9.1.] Register setting overview
[AK8859VQ]
[9.1.1.] Sub Address 0x00 “Input Channel Select Register (R/W)”
Input signal channel selection and clock mode selection register.
Sub Address: 0x00
bit 7
bit 6
CLKMD Reserved
Default Value
0
0
bit 5
Reserved
0
bit 4
Reserved
0
bit 3
Reserved
0
bit 2
Reserved
Default Value: 0x00
bit 1
bit 0
AINSEL1 AINSEL0
0
0
0
Input Channel Select Register Definition
Bit ^Register
R/W
Name
bit 0 AINSEL0
~
~
bit 1 AINSEL1
Analog Input
R/W
Select
bit 2
~ Reserved
bit 6
Reserved R/W
bit 7 CLKMD
Clock Mode R/W
*Clamp and ADC block is power-downed.
Definition
Input video signal selection
[ AINSEL1 : AINSEL0 ]
[00]: AIN1 (CVBS)
[01]: AIN2 (CVBS)
[10]: AIN1(Y) / AIN2(C) (S-video)
[11]: No input setting (Analog circuit is set to power-down*)
Reserved
Clock mode selection
[0]: For crystal
[1]: External clock input (clock generator etc.)
In used with AINSEL[1:0]=[11], Ouput data is depend on NSIGMD[1:0]–bit. However, in used with
NSIGMD[1:0]=[10], DATA[7:0]-pin, HD-pin, VD_F-pin, VAR-pin and VARSUB-pin output Low.
MS1178-E-00
AKM Confidential
- 47 -
2010/04