AK7758VN Datasheet, PDF (5/32 Pages) Asahi Kasei Microsystems – DSP with Stereo CODEC + Mic/Lineout Amp

[AK7758]
4.2. DSP Block Diagram
Pointer CP0, CP1
DP0, DP1
Coefficient RAM
(CRAM)
4096w x 24-Bit
Data RAM (DRAM)
4096w x 28-Bit(24.4f)
CBUS(24-Bit)
DLP0, DLP1
OFREG
32w x 14-Bit
Delay RAM (DLRAM)
16384w x 28-Bit(24.4f)
DBUS(28-Bit)
MPX24
MPX24
X
Y
Multiply
24 x 24 → 48-Bit
48-Bit
28-Bit
52-Bit
MUL DBUS
SHIFT
48-Bit
A
B
ALU
52-Bit
Overflow Margin: 4-Bit
52-Bit
DR0  3
52-Bit
Over Flow Data
Generator
Micon I/F
Control
Serial I/F
DEC
Program RAM
(PRAM)
6144w x 36-Bit
PC
Stack : 5level(max)
TMP 12 x 28-Bit
PTMP(LIFO) 6 x 28-Bit
2 x 16/20/24-Bit DIN6
2 x 16/20/24-Bit DIN5
2 x 16/20/24-Bit DIN4
2 x 16/20/24-Bit DIN3
2 x 16/20/24-Bit DIN2
2 x 16/20/24-Bit DIN1
2 x 16/20/24-Bit DOUT6
2 x 16/20/24-Bit DOUT5
2 x 16/20/24-Bit DOUT4
2 x 16/20/24-Bit DOUT3
2 x 16/20/24-Bit DOUT2
2 x 16/20/24-Bit DOUT1
28bit x fifo16
CTMP (Sub DSP)
Division 2424→24 _{Peak Detector}
Figure 2. DSP Block Diagram
016003563-E-02-PB
-5-
2016/09