AK7758VN Datasheet, PDF (23/32 Pages) Asahi Kasei Microsystems – DSP with Stereo CODEC + Mic/Lineout Amp

[AK7758]
8.5.2. Power Down
(Ta= -40~85°C; AVDD=LVDD=3.0~3.6V, TVDD1/2=1.7~3.6V, DVDD=1.14~1.3V, AVSS=DVSS=0V)
Parameter
Symbol
Min.
Typ.
Max.
Unit
PDN Pulse Width (Note 45)
tRST
600
ns
Note 45. The PDN pin must be set “L” when power up the AK7758.
PDN
tRST
VIL
Figure 7. Reset Timing
8.5.3. Serial Data Interface (SDIN1/2/3, SDOUT1/2/3/4) Power Down
(Ta= -40~85°C; AVDD=LVDD=3.0~3.6V, TVDD1/2=1.7~3.6V, DVDD=1.14~1.3V, AVSS=DVSS=0V,
CL=20pF)
Parameter
Symbol Min.
Typ.
Max. Unit
Slave Mode
Delay Time from BICK “↑” to LRCK (Note 46)
tBLRD 20
ns
Delay Time from LRCK to BICK “↑” (Note 46)
tLRBD 20
ns
Serial Data Input Latch Setup Time
tBSIDS 10
ns
Serial Data Input Latch Hold Time
tBSIDH 10
ns
Delay Time from LRCK to Serial Data Output (Note 47) tLRD
30 ns
Delay Time from BICK “↓” to Serial Data Output (Note 48) tBSOD
30 ns
Master Mode
BICK Frequency
fBCLK
32,48,64,
128,256
fs
BICK Duty Cycle
50
%
Delay Time from BICK “↓” to LRCK (Note 48)
tMBL -12
12 ns
Serial Data Input Latch Setup Time
tBSIDS 20
ns
Serial Data Input Latch Hold Time
tBSIDH 20
ns
Delay Time from LRCK to Serial Data Output (Note 47) tLRD
20 ns
Delay Time from BICK “↓” to Serial Data Output (Note 48) tBSOD
20 ns
SDINx → SDOUTy (x=1,2,3, y=1,2,3,4,)
Delay Time from SDINn to SDOUTn Output
tIOD
2
fs
Note 46. BICK edge must not occur at the same time as LRCK edge.
If BICK polarity was inverted, the counting edge of BICK will be “↓”.
Note 47. Except I²S.
Note 48. When the polarity of BICK is inverted, delay time is from BICK “↑”.
Note 49. SDINx(x=1~3) and SDOUTy (y=1~4) should be set to the same Sync Domain. There are the
values when the input data of SDOUTy is set to SDINx.
SDOUTy
SDINx
tIOD
Figure 8. Serial Interface Delay Time from SDINx to SDOUTy Output
50%TVDD
VIH
D _VIH
D^VIL
D
016003563-E-02-PB
- 23 -
2016/09