AK7758VN Datasheet, PDF (22/32 Pages) Asahi Kasei Microsystems – DSP with Stereo CODEC + Mic/Lineout Amp

[AK7758]
8.5. Switching Characteristics
8.5.1. System Clock
(Ta= -40~85°C; AVDD=3.0~3.6V, TVDD1/2=1.7~3.6V, DVDD=1.14~1.3V, AVSS=DVSS=0V,
CL=20pF)
Parameter
Symbol
Min.
Typ.
Max. Unit
with Crystal Oscillator
Input Frequency
fXTI
11.2896
18.432 MHz
with External Clock
Duty Cycle
Input Frequency
40
50
60
%
fXTI
11.0
18.6 MHz
LRCK Frequency
(Note 43)
fs
8
48
kHz
BICK Frequency
(Note 44)
Normal Interface
TDM Interface
High Level Width tBCLKH
128
Low Level Width tBCLKL
128
Frequency
fBCLK
0.23
High Level Width tBCLKH
32
3.072
ns
ns
3.1
MHz
ns
Low Level Width tBCLKL
32
ns
Frequency
fBCLK
1.8
12.288 12.3 MHz
Note 43. LRCK frequency and sampling rate (fs) should be the same.
Note 44. When BICK is the source of the master clock, it should be synchronized to LRCK and have
stable frequency.
1/fXTI
1/fXTI
XTI
tXTI=1/fXTI
VIH
VIL
LRCK
BICK
1/fs
1/fs
ts=1/fs
VIH
VIL
1/fBCLK
1/fBCLK
tBCLK=1/fBCLK
VIH
VIL
tBCLKH tBCLKL
Figure 6. System Clock Timing
016003563-E-02-PB
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2016/09