AK7758VN Datasheet, PDF (25/32 Pages) Asahi Kasei Microsystems – DSP with Stereo CODEC + Mic/Lineout Amp

[AK7758]
8.5.4. SPI Interface
8.5.4.1. Clock Reset (CKRESTN bit = “0”)
(Ta= -40~85°C; AVDD=LVDD=3.0~3.6V, TVDD1/2=1.7~3.6V, DVDD=1.14~1.3V, AVSS=DVSS=0V,
CL=20pF)
Parameter
Symbol Min.
Typ.
Max. Unit
Microcontroller Interface Signal
SCLK Frequency (Note 50)
fSCLK
3.5 MHz
SCLK Low Level Width
tSCLKL 120
ns
SCLK High Level Width
tSCLKH 120
ns
Microcontroller → AK7758
CSN High Level Width
tWRQH 300
ns
Time from CSN “↑” to PDN “↑”
tRST
360
ns
Time from PDN“↑” to CSN “↓”
tIRRQ
1
ms
Time from CSN“↓” to SCLK“↓”
tWSC
360
ns
Time from SCLK“↑” to CSN“↑”
tSCW
480
ns
SI Latch Setup Time
tSIS
40
ns
SI Latch Hold Time
tSIH
40
ns
AK7758 → Microcontroller
SO Output Delay Time from SCLK “↓”
tSOS
40
ns
Note 50. SCLK frequency becomes 7 MHz when accessing control registers.
8.5.4.2. PLL Lock (CKRESTN bit = “1”)
(Ta= -40~85°C; AVDD=LVDD=3.0~3.6V, TVDD1/2=1.7~3.6V, DVDD=1.14~1.3V, AVSS=DVSS=0V,
CL=20pF)
Parameter
Symbol Min.
Typ.
Max. Unit
Microcontroller Interface Signal
SCLK Frequency (Note 51)
fSCLK
7
MHz
SCLK Low Level Width
tSCLKL
60
ns
SCLK High Level Width
tSCLKH 60
ns
Microcontroller → AK7758
CSN High Level Width
tWRQH 150
ns
Time from CSN “↑” to PDN “↑”
tRST
180
ns
Time from PDN“↑” to CSN “↓”
tIRRQ
1
ms
Time from CSN“↓” to SCLK“↓”
tWSC
150
ns
Time from SCLK“↑” to CSN“↑”
tSCW
240
ns
SI Latch Setup Time
tSIS
20
ns
SI Latch Hold Time
tSIH
20
ns
AK7758 → Microcontroller
SO Output Delay Time from SCLK “↓”
tSOS
40
ns
Note 51. It takes 10ms at maximum until PLL is locked, after setting CKRESTN bit to “1” from “0”.
016003563-E-02-PB
- 25 -
2016/09