AK4368 Datasheet, PDF (49/58 Pages) Asahi Kasei Microsystems – PLL & HP-AMP DAC

ASAHI KASEI
[AK4368]
Addr
02H
Register Name
Clock Control
R/W
Default
D7
D6
D5
D4
D3
D2
D1
D0
0
0
M/S MCKAC BF
PS0
PS1 MCKO
RD
RD R/W R/W R/W R/W R/W R/W
0
0
0
0
0
0
0
0
MCKO: MCKO৴߸Λ੍͢·͠ޚɻ
0: Disable (Default)
1: Enable
PS1-0: MCKOप೾਺ઃఆ
PLL mode: Table 3
EXT mode: Table 7
BF: ϚελϞʔυ࣌ͷBICKप೾਺ͷઃఆɻεϨʔϒϞʔυ࣌ɺ͜ͷϏοτ͸ແޮʹͳΓ·͢ɻ
0: 32fs (Default)
1: 64fs
MCKAC: MCLKೖྗϞʔυઃఆ
0: CMOSೖྗ (Default)
1: ACΧοϓϦϯάೖྗ
M/S: Ϛελ/εϨʔϒϞʔυઃఆ
0: εϨʔϒϞʔυ (Default)
1: ϚελϞʔυ
Addr
03H
Register Name
Mode Control 0
R/W
Default
D7
D6
D5
D4
D3
0 MONO1 MONO0 BCKP LRP
RD R/W R/W R/W R/W
0
0
0
0
0
DIF2-0: ΦʔσΟΦσʔλΠϯλϑΣʔεϑΥʔϚοτͷઃఆ (Table 11)
Default: “010” (Mode 2)
LRP: LRCKۃੑઃఆ(εϨʔϒϞʔυ࣌)
0: ௨ৗ(Default)
1: ൓స
BCKP: BICKۃੑઃఆ(εϨʔϒϞʔυ࣌)
0: ௨ৗ(Default)
1: ൓స
MONO1-0: ϛΩγϯάઃఆ (Table 21)
Default: “00” (LR)
D2
DIF2
R/W
0
D1
DIF1
R/W
1
D0
DIF0
R/W
0
MS0409-J-01
- 49 -
2005/08