AK4368 Datasheet, PDF (12/58 Pages) Asahi Kasei Microsystems – PLL & HP-AMP DAC

ASAHI KASEI
[AK4368]
εΠονϯάಛੑ
(Ta=25°C; AVDD, DVDD, PVDD, HVDD=1.6 ∼ 3.6V; CL = 20pF)
Parameter
Symbol
min
typ
Master Clock Input Timing
Frequency (PLL mode)
(EXT mode)
Pulse Width Low (Note 19)
Pulse Width High (Note 19)
AC Pulse Width (Note 20)
fCLK
11.2896
-
fCLK
2.048
-
tCLKL 0.4/fCLK
-
tCLKH 0.4/fCLK
-
tACW
18.5
-
LRCK Timing
Frequency
Duty Cycle: Slave Mode
Master Mode
fs
8
44.1
Duty
45
-
Duty
-
50
MCKO Output Timing (PLL mode)
Frequency
fCLKO
0.256
-
Duty Cycle (Except fs=32kHz, PS1-0= “00”)
dMCK
40
-
(fs=32kHz, PS1-0= “00”)
dMCK
-
33
Serial Interface Timing (Note 21)
Slave Mode (M/S bit = “0”):
BICK Period
tBCK
312.5
-
BICK Pulse Width Low
tBCKL
100
-
Pulse Width High
tBCKH
100
-
LRCK Edge to BICK “↑” (Note 22)
tLRB
50
-
BICK “↑” to LRCK Edge (Note 22)
tBLR
50
-
SDATA Hold Time
tSDH
50
-
SDATA Setup Time
tSDS
50
-
Master Mode (M/S bit = “1”):
BICK Frequency (BF bit = “1”)
(BF bit = “0”)
fBCK
-
64fs
fBCK
-
32fs
BICK Duty
BICK “↓” to LRCK
SDATA Hold Time
SDATA Setup Time
dBCK
-
50
tMBLR
−50
-
tSDH
50
-
tSDS
50
-
Control Interface Timing (3-wire Serial mode)
CCLK Period
tCCK
200
-
CCLK Pulse Width Low
tCCKL
80
-
Pulse Width High
CDTI Setup Time
CDTI Hold Time
CSN “H” Time
CSN “↑” to CCLK “↑”
CCLK “↑” to CSN “↑”
tCCKH
80
-
tCDS
40
-
tCDH
40
-
tCSW
150
-
tCSS
50
-
tCSH
50
-
max
27
12.288
-
-
-
48
55
-
12.288
60
-
Units
MHz
MHz
ns
ns
ns
kHz
%
%
MHz
%
%
-
ns
-
ns
-
ns
-
ns
-
ns
-
ns
-
ns
-
Hz
-
Hz
-
%
50
ns
-
ns
-
ns
-
ns
-
ns
-
ns
-
ns
-
ns
-
ns
-
ns
-
ns
Note 19. ACΧοϓϦϯά࣌Λআ͘ɻ
Note 20. MCKIʹରͯ͠௚ྻʹίϯσϯαΛ઀ଓ͠ɺ఍߅Λάϥϯυʹରͯ͠઀ଓͨ͠৔߹ͷάϥϯυʹର͢
Δύϧε෯ɻ(Figure 3ࢀর)
Note 21. γϦΞϧσʔλΠϯλϑΣʔεͷ߲Λࢀরͯ͠Լ͍͞ɻ
Note 22. ͜ͷ֨ن஋͸ LRCKͷΤοδͱBICKͷ “↑”͕ॏͳΒͳ͍Α͏ʹنఆ͍ͯ͠·͢ɻ
MS0409-J-01
- 12 -
2005/08