AK4368 Datasheet, PDF (22/58 Pages) Asahi Kasei Microsystems – PLL & HP-AMP DAC

ASAHI KASEI
[AK4368]
„
γϦΞϧσʔλΠϯλϑΣʔε

SDATA, BICK, LRCKͷ3pinΛ࢖༻ͯ͠֎෦ͷγεςϜͱΠϯλϑΣʔε͠·͢ɻ5छྨͷσʔλϑΥʔϚο
τ(Table 11)͕ DIF2-0 bitsͰબ୒Ͱ͖·͢ɻMode 0 ͸طଘͷ16bitDACͼٴσΟδλϧϑΟϧλͱ׵ޓੑ͕͋
Γ·͢ɻMode 1 ͸Mode 0 ͷ20bit൛Ͱ͢ɻMode 4 ͸Mode 0 ͷ24bit൛Ͱ͢ɻMode 2 ͸౰ࣾADC΍छʑͷ൚༻
DSP ͷγϦΞϧϙʔτͱ׵ޓੑ͕͋Γ·͢ɻMode 3 ͸I²SΠϯλϑΣʔεͱ׵ޓੑ͕͋Γ·͢ɻBICK≥48fs
࣌Mode 2 ͱ 3 Ͱ16bitσʔλΛೖྗ͢Δ৔߹͸ɺLSB ʹଓ͚ͯ17∼24bit໨ʹ8ݸͷ “0”Λೖྗ͠ɺ20bitσʔλͷ
৔߹͸ LSB ʹଓ͚ͯ21∼24bit໨ʹ4ݸͷ “0”Λೖྗ͠·͢ɻ
ϚελϞʔυͰBICK=32fs(BF bit = “0”)ͷ৔߹ɺΦʔσΟΦϑΥʔϚοτͷMode 1, 2ʹ͸ରԠ͍ͯ͠·ͤΜɻ
Mode
0
1
2
3
4
DIF2
0
0
0
0
1
DIF1
0
0
1
1
0
DIF0
0
1
0
1
0
ϑΥʔϚοτ
BICK
0: 16bit, ޙ٧Ί
32fs ≤ BICK ≤ 64fs
1: 20bit, ޙ٧Ί
40fs ≤ BICK ≤ 64fs
2: 24bit, લ٧Ί
3: I²S׵ޓ
48fs ≤ BICK ≤ 64fs
BICK=32fs or 48fs ≤ BICK ≤ 64fs
4: 24bit, ޙ٧Ί
48fs ≤ BICK ≤ 64fs
Table 11. ΦʔσΟΦϑΥʔϚοτ
ਤ
Figure 15
Figure 16
Figure 17
Figure 18
Figure 16
Default
LRCK
BICK
(32fs)
SDATA
Mode 0
BICK
15 14
6 5 4 3 2 1 0 15 14
6 5 4 3 2 1 0 15 14
SDATA
Mode 0
Don’t care
15:MSB, 0:LSB
15 14
0 Don’t care
15 14
0
Lch Data
Rch Data
Figure 15. Mode 0 λΠϛϯά(LRP = BCKP bits = “0”)
LRCK
BICK
SDATA
Mode 1
Don’t care
19:MSB, 0:LSB
19
0 Don’t care
19
0
SDATA
Don’t care 23 22 21 20 19
0 Don’t care 23 22 21 20 19
0
Mode 4
23:MSB, 0:LSB
Lch Data
Rch Data
Figure 16. Mode 1, 4 λΠϛϯά(LRP = BCKP bits = “0”)
MS0409-J-01
- 22 -
2005/08