AK4368 Datasheet, PDF (13/58 Pages) Asahi Kasei Microsystems – PLL & HP-AMP DAC

ASAHI KASEI
[AK4368]
Parameter
Symbol
min
typ
max
Control Interface Timing (I²C Bus mode): (Note 23)
SCL Clock Frequency
fSCL
-
-
400
Bus Free Time Between Transmissions
tBUF
1.3
-
-
Start Condition Hold Time (prior to first clock pulse) tHD:STA
0.6
-
-
Clock Low Time
tLOW
1.3
-
-
Clock High Time
tHIGH
0.6
-
-
Setup Time for Repeated Start Condition
tSU:STA
0.6
-
-
SDA Hold Time from SCL Falling (Note 24)
tHD:DAT
0
-
-
SDA Setup Time from SCL Rising
tSU:DAT
0.1
-
-
Rise Time of Both SDA and SCL Lines
tR
-
-
0.3
Fall Time of Both SDA and SCL Lines
tF
-
-
0.3
Setup Time for Stop Condition
tSU:STO
0.6
-
-
Pulse Width of Spike Noise Suppressed by Input Filter tSP
0
-
50
Power-down & Reset Timing
PDN Pulse Width (Note 25)
tPD
150
-
-
Note 23. I²C͸Philips Semiconductorsͷొ࿥঎ඪͰ͢ɻ
Note 24. σʔλ͸࠷௿300ns (SCLͷཱͪԼ͕Γ࣌ؒ)ͷؒอ࣋͞Εͳ͚Ε͹ͳΓ·ͤΜɻ
Note 25. ݯి౤ೖ࣌͸PDN pinΛ “L” ͔Β “H” ʹ͢Δ͜ͱͰϦηοτ͕͔͔Γ·͢ɻ
Units
kHz
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
ns
ns
MS0409-J-01
- 13 -
2005/08