AK4620A Datasheet, PDF (4/42 Pages) Asahi Kasei Microsystems – 24 BIT 192KHZ AUDIO CODEC WITH IPGA

ASAHI KASEI
[AK4620A]
PIN/FUNCTION
No. Pin Name I/O Function
1 VCOM
Common Voltage Output Pin, VA/2
O
Bias voltage of ADC inputs and DAC outputs.
2 AINR+
I Rch Positive Input Pin
I Rch Negative Input Pin (when ADMODE pin=“H”)
3 AINR-
No Connect pin (when ADMODE pin=“L”)
I
No internal bonding. This pin should be open.
4 AINL+
I Lch Positive Input Pin
I Lch Negative Input Pin (when ADMODE pin=“H”)
5 AINL-
No Connect pin (when ADMODE pin=“L”)
I
No internal bonding. This pin should be open.
Voltage Reference Input Pin, VA
6 VREF
I
Used as a voltage reference by ADC & DAC. VREF is connected externally to filtered
VA.
7 AGND
- Analog Ground Pin
8 VA
- Analog Power Supply Pin, 4.75 ∼ 5.25V
Parallel/Serial Mode Select Pin
9 P/S
I
“L”: Serial Mode, “H”: Parallel Mode
Do not change this pin during PDN pin = “H”.
10 MCLK
I Master Clock Input Pin
LRCK
11
DSDR
I Input/Output Channel Clock Pin (in Parallel mode or when D/P bit=“0” in Serial Mode)
I DSD Rch Data Input Pin (when D/P bit=“1” in Serial Mode)
BICK
12
DCLK
I Audio Serial Data Clock Pin (in Parallel mode or when D/P bit=“0” in Serial Mode)
I DSD Clock Pin (when D/P bit=“1” in Serial Mode)
13 SDTO
O Audio Serial Data Output Pin
SDTI
14
DSDL
I Audio Serial Data Input Pin (in Parallel mode or when D/P bit=“0” in Serial Mode)
I DSD Lch Data Input Pin (when D/P bit=“1” in Serial Mode)
OVFR
15
DZFR
O Rch Over Flow Flag Pin (in Parallel mode or when ZOS bit=“0” in Serial Mode)
O Rch Zero Detection Flag Pin (when ZOS bit=“1” in Serial Mode)
OVFL
16
DZFL
O Lch Over Flow Flag Pin (in Parallel mode or when ZOS bit=“0” in Serial Mode)
O Lch Zero Detection Flag Pin (when ZOS bit=“1” in Serial Mode)
CDTI
17
CKS0
I Control Data Input Pin (in Serial Mode)
I Master Clock Select Pin (in Parallel Mode)
CCLK
18
CKS1
I Control Data Clock Pin (in Serial Mode)
I Master Clock Select Pin (in Parallel Mode)
CSN
I Chip Select Pin in Serial Mode (in Serial Mode)
19
DIF
Digital Audio Interface Select Pin (in Parallel Mode)
I
“L”: 24bit MSB justified, “H”: I²S compatible
20 DFS0
I Double Speed Sampling Mode Pin
21 PDN
Power-Down Mode Pin
I
“L”: Power down reset and initialize the control register, “H”: Power up
22 DEM0
I De-emphasis Control Pin
Analog Input Mode Select Pin
23 ADMODE I
“L”: Single-ended Input & IPGA Enable
“H”: Differential Input & IPGA Bypass
MS0368-E-00
-4-
2004/12