AK4620A Datasheet, PDF (31/42 Pages) Asahi Kasei Microsystems – 24 BIT 192KHZ AUDIO CODEC WITH IPGA

ASAHI KASEI
[AK4620A]
Addr Register Name
01H Reset Control
DEFAULT
D7
D6
D5
D4
D/P DCKS DCKB
0
0
0
0
0
D3
AML
0
D2
AMR
0
D1
D0
RSTAD RSTDA
0
0
RSTDA: DAC reset
0: Reset (Default)
1: Normal Operation
“0” resets the internal timing and the AOUTs go to VCOM voltage immediately. The contents of all registers
are not initialized and enabled to write to the registers. After exiting the power down mode, the OATTs fade in
the setting values of the control register (06H & 07H). The analog outputs should be muted externally since
pop noise may occur when entering to and exiting from this mode.
RSTAD: ADC reset
0: Reset (Default)
1: Normal Operation
“0” resets the internal timing and then SDTO goes to “L” immediately. The IPGAs also go “00H”, but the
contents of all registers are not initialized and enabled to write to the register. After exiting the power down
mode, the IPGAs fade in the setting value of the control register (04H & 05H). At that time, the ADCs output
“0” during first 516 LRCK cycles.
AML, AMR: default “0” (see Table 16)
DCKB: Polarity of DCLK (DSD Only)
0: DSD data is available upon DCLK falling edge. (Default)
1: DSD data is available upon DCLK rising edge.
DCKS: Master Clock Frequency Select at DSD mode (DSD only)
0: 512fs (Default)
1: 768fs
D/P: DSD/PCM Mode Select
0: PCM mode (Default)
1: DSD mode
Addr Register Name
02H Clock and Format Control
DEFAULT
D7
DIF2
0
D6
DIF1
1
D5
DIF0
0
D4
CMODE
0
D3
CKS1
0
D2
CKS0
0
D1
DFS1
0
D0
DFS0
0
DFS1-0: Sampling Speed Control (see Table 2)
Default: Normal speed
CMODE, CKS1-0: Master Clock Frequency Select (see Table 3)
Default: 256fs
DIF2-0: Audio data interface modes (see Table 9)
000: Mode 0
001: Mode 1
010: Mode 2
011: Mode 3
100: Mode 4
Default: 24bit MSB justified for both ADC and DAC
MS0368-E-00
- 31 -
2004/12