AK4620A Datasheet, PDF (30/42 Pages) Asahi Kasei Microsystems – 24 BIT 192KHZ AUDIO CODEC WITH IPGA

ASAHI KASEI
[AK4620A]
„ Register Definitions
Addr Register Name
00H Power Down Control
DEFAULT
D7
D6
D5
D4
SLOW DZFB ZOE ZOS
0
0
0
0
D3
D2
D1
D0
0 PWVR PWAD PWDA
0
1
1
1
PWDA: DAC power down
0: Power down
1: Power up (Default)
“0” powers down only the DAC section and then the AOUTs go to Hi-Z immediately. The contents of all
registers are not initialized and enabled to write to the registers. After exiting power down mode, the OATTs
fade in/out the setting value of the control register (06H & 07H). The analog output should be muted externally
as some pop noise may occur when entering and exiting this mode.
PWAD: ADC power down
0: Power down
1: Power up (Default)
“0” powers down only the ADC and then the SDTO goes “L” immediately. The IPGAs also go “00H”, but the
contents of all registers are not initialized and enabled to write to the registers. After exiting power down
mode, the IPGAs fade in the setting value of the control register (04H & 05H). At that time, the ADCs output
“0” during first 516 LRCK cycles.
PWVR: Vref power down
0: Power down
1: Power up (Default)
“0” powers all sections down and then both ADC and DAC do not operate. The contents of all register values
are not initialized and enabled to write to the registers. When PWAD and PWDA bits go to “0” and PWVR bit
goes to “1”, only the VREF section can be powered up.
ZOS: Zero-detection/ Overflow-detection control for #15 and 16 pins.
0: Overflow detection for ADC input (Default)
1: Zero detection for DAC input.
ZOE: Zero-detection / Overflow-detection Disable
0: Enable (Default)
1: Disable. Outputs “L”.
DZFB: Inverting Enable of DZF
0: DZF goes “H” at Zero Detection (Default)
1: DZF goes “L” at Zero Detection
SLOW: DAC Slow Roll-off Filter Enable
0: Sharp Roll-off Filter (Default)
1: Slow Roll-off Filter
MS0368-E-00
- 30 -
2004/12