AK4620A Datasheet, PDF (29/42 Pages) Asahi Kasei Microsystems – 24 BIT 192KHZ AUDIO CODEC WITH IPGA

ASAHI KASEI
[AK4620A]
„ Register Map
Addr
00H
01H
02H
03H
04H
05H
06H
07H
Register Name
Power Down Control
Reset Control
Clock and Format Control
Deem and Volume Control
Lch IPGA Control
Rch IPGA Control
Lch ATT Control
Rch ATT Control
D7
SLOW
D/P
DIF2
SMUTE
IPGL7
IPGR7
ATTL7
ATTR7
D6
DZFB
DCKS
DIF1
HPRN
IPGL6
IPGR6
ATTL6
ATTR6
D5
ZOE
DCKB
DIF0
HPLN
IPGL5
IPGR5
ATTL5
ATTR5
D4
ZOS
0
CMODE
ZCEI
IPGL4
IPGR4
ATTL4
ATTR4
D3
0
AML
CKS1
ZTM1
IPGL3
IPGR3
ATTL3
ATTR3
D2
PWVR
AMR
CKS0
ZTM0
IPGL2
IPGR2
ATTL2
ATTR2
D1
PWAD
RSTAD
DFS1
DEM1
IPGL1
IPGR1
ATTL1
ATTR1
D0
PWDA
RSTDA
DFS0
DEM0
IPGL0
IPGR0
ATTL0
ATTR0
Note: Data should not be written to addresses 08H through 1FH.
PDN pin = “L” resets the registers to their default values.
„ Control Register Setup Sequence
When the PDN pin goes “L” to “H” upon power-up etc., the AK4620A will be ready for normal operation by the next
sequence. In this case, all control registers are set to default values and the AK4620A is in the reset state.
(1) Set the clock mode and the audio data interface mode.
(2) Cancel the reset state by setting RSTAD bit or RSTDA bit to “1”. Refer to Reset Contorl Register (01H).
(3) ADC output and DAC output should be muted externally until canceling each reset state.
The clock mode should be changed after setting RSTAD bit and RSTDA bit to “0”. At that time, ADC outputs and DAC
outputs should be muted externally.
MS0368-E-00
- 29 -
2004/12