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AK4620A Datasheet, PDF (18/42 Pages) Asahi Kasei Microsystems – 24 BIT 192KHZ AUDIO CODEC WITH IPGA | |||
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ASAHI KASEI
[AK4620A]
CMODE bit
0
0
0
0
1
1
MCLK
MCLK
MCLK
CKS1 bit CKS0 bit Normal Speed
Double Speed
Quad Speed
(DFS1-0 = â00â)
(DFS1-0 = â01â) (DFS1-0 = â10â)
0
0
256fs
N/A
N/A
0
1
512fs
256fs
128fs
1
0
1024fs
512fs
256fs
1
1
N/A
Auto Setting Mode (*)
N/A
0
0
384fs
N/A
N/A
0
1
768fs
384fs
192fs
Table 3. Master clock frequency in serial mode (â*â: refer to Table 4)
Default
The Auto Setting Mode detects MCLK/LRCK ratio and selects Normal/Double/Quad speed mode automatically.
MCLK/LRCK ratio
Mode
Sampling Rate
512 or 768
Normal speed
32kHz-54kHz
256 or 384
Double speed
54kHz-108kHz
128 or 192
Quad speed
108kHz-216kHz
Table 4. Auto Setting Mode in serial mode (DFS1-0 = â01â, CMODE bit = â1â, CKS1-0 bit = â11â)
1-2. Parallel mode (P/S pin= âHâ)
As shown in Table 5, Table 6 and Table 7, select the MCLK frequency with the CKS0-1 and DFS0 pins. These
pins should be changed when the PDN pin = âLâ.
DFS0 pin
L
H
Mode
Sampling Rate
Normal speed
32kHz-54kHz
Double speed
54kHz-108kHz
Table 5. Sampling speed in parallel mode
MCLK
MCLK
CKS1 pin CKS0 pin Normal Speed
Double Speed
(DFS0 pin = âLâ) (DFS0 pin = âHâ)
L
L
256fs
N/A
L
H
512fs
256fs
H
L
384fs
Auto Setting Mode (*)
H
H
1024fs
512fs
Table 6. Master clock frequency in parallel mode (â*â; refer to Table 7.)
The Auto Setting Mode detects MCLK/LRCK ratio and selects Normal/Double/Quad speed mode automatically.
MCLK/LRCK ratio
Mode
Sampling Rate
512 or 768
Normal speed
32kHz-54kHz
256 or 384
Double speed
54kHz-108kHz
128 or 192
Quad speed
108kHz-216kHz
Table 7. Auto Setting Mode in parallel mode (DFS0 pin = âHâ, CKS1 pin = âHâ, CKS0 pin = âLâ)
MS0368-E-00
- 18 -
2004/12
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