AK4620A Datasheet, PDF (26/42 Pages) Asahi Kasei Microsystems – 24 BIT 192KHZ AUDIO CODEC WITH IPGA

ASAHI KASEI
[AK4620A]
„ Power Down & Reset
The ADC and DAC of AK4620A are placed in power-down mode by bringing the PDN pin = “L”. Each digital filter is
also reset at the same time. The internal register values are initialized by bringing PDN pin to “L”. This reset should
always be done after power-up. As both control registers of the ADC and the DAC go to the reset state (RSTAD bit =
RSTDA bit = “0”), each register should be cleared after performing the reset. In the case of the ADC, an analog
initialization cycle starts after exiting the power-down or reset state. The output data (SDTO) is available after 516 cycles
of LRCK clock. This initialization cycle does not affect the DAC operation. Power down mode can be also controlled by
the registers (PWAD bit, PWDA bit).
Pow er Supply
PDN pin
RSTAD(register)
RSTDA(register)
PWAD(register)
PWDA(register)
PWVR(register)
ADC Internal State
IATT
SDTO
DAC Internal State
OATT
AOUT
External Mute
Ex amp le
External clocks
PD Reset INITA
Normal
PD INITA
Normal
00H 00H → XXH
XXH
00H 00H → XXH XXH
“0”
FI
Output
“0”
FI Output
PD
Reset
Normal
PD Normal
FFH
FFH (1)
FFH → XXH
XXH
XXH(2) XXH _→ YYH YYH
Hi-z
VCOM
*
FADE
*
Output
Hi-z FADE
**
MCLK, LRCK, BICK
The clocks can be stopped.
• INITA: Initializing period of ADC analog section (516/fs).
• PD:
Power down state. The contents of all registers are held.
• XXH, YYH: The current value in ATT registers.
• FI:
Fade in. After exiting power down and reset state, ATT value fades in.
• FADE: After exiting power down and reset state, ATT value fades in/out.
(1) When RSTDA is “L” and OATT value is written to “XXH”, OATT value changes from FFH
to XXH according to fade operation.
(2) When PWDA is “L” and OATT value is written to “YYH”, OATT value changes from XXH
to YYH according to fade operation.
• AOUT: Some pop noise may occur at “*”.
Figure 11. Reset & Power down sequence in serial mode
MS0368-E-00
- 26 -
2004/12