AK4620A Datasheet, PDF (27/42 Pages) Asahi Kasei Microsystems – 24 BIT 192KHZ AUDIO CODEC WITH IPGA

ASAHI KASEI
[AK4620A]
In parallel mode, both ADC and DAC are powered up with releasing internal reset state when PDN pin is set to “H”.
When PDN pin is “L”, IATT is set to “00H (Mute)”. After exiting power down mode, IATTs fade in to “80H (0dB)”. At
that time, ADC s output “0” during first 516/fs cycles. DAC does not have the initialization cycle and the operation of
fade-in.
Power Supply
PDN pin
ADC Internal State
PD INITA
Normal
PD
INITA
Normal
IATT
00H 00HÆ80H
80H
00H 00HÆ80H
80H
SDTO
DAC Internal State
“0” FI
PD
Output
Normal
“0”
PD
FI
Output
Normal
AOUT
External Mute
Example
External clocks
Hi-Z
*
Output
MCLK, LRCK, BICK
Hi-Z
*
*
Output
MCLK, LRCK, BICK
• INITA:
• PD:
• FI:
• AOUT:
The clocks can be stopped.
Initializing period of ADC analog section (516/fs).
Power down state.
Fade in. After exiting power down and reset state, ATT value fades in.
Some pop noise may occur at “*”.
Figure 12. Reset & Power Down Sequence in parallel mode
MS0368-E-00
- 27 -
2004/12