AK2400 Datasheet, PDF (4/52 Pages) Asahi Kasei Microsystems – High integrated receiver for PMR-LMR

[AK2400]
Function
Block
PLL SYNTH
1stMIX
PGA0+2ndMIX
AGC+BPF
IFBUF
Divider
LIMITER
DISCRI
Noise AMP
Noise Rectifier
Comparator
RSSI
AGND+VIREF
Control Logic
ADC
Description
The Delta-Sigma Fractional-N PLL (Phase Locked Loop) frequency synthesizer by the
external VCO and the loop filter.
1st Mixer to convert the RFIN signal down to IF frequency by 1st LO signal.
2nd Mixer to convert the IFIP signal down to 450kHz by 2ndLO signal.
The circuit composed of AGC and BPF, where the desired signal is amplified and
spurious components included in the signal from the 2nd-mixer are eliminated.
The circuit to output filtered signal by AGC+BPF.
The circuit to divide the signal from LO2NDIN pin.
The circuit to amplify the signal filtered at the AGC+BPF stage and generate
rectangular wave.
The demodulator circuit with PLL FM detector, where the audio signal is recovered.
The amplifiers to compose the Band-pass filter for noise squelch.
The rectification circuit to detect the noise level.
The circuit to compare the noise level with reference voltage level.
The circuit to indicate the Received Signal Strength Indicator (RSSI) by generating a
DC voltage corresponding to the input level from Limiter.
The circuit to generate internal reference voltage.
The control register controls the status of internal condition by serial data that consists
of 1 instruction bit, 5 address bits and 18 data bits.
12bits 1MSPS A/D converter.
Pin assignment
CPVSS
SWIN
CPZ
CP
PVDD
RFINP
RFINN
PVSS
VREF1
BIAS3
BIAS2
BIAS1
LOINP
LOINN
42 41 40 39 38 37 36 35 34 33 32 31 30 29
43
28
44
27
45
26
46
25
47
24
48
23
49
50
51
52
53
54
55
56
123456
78
22
21
20
19
18
17
16
15
9 10 11 12 13 14
ADIN
IFOUT
RSSIOUT
NRECTO
NAMPO
NAMPI
AUDIOOUT
DISOUT
PDOUT
BIAS4
AGNDIN
AGNDOUT
VREFA
AVDD
Figure 2 Pin assignment
Note) The exposed pad at the center of the backside should be connected to ground.
014008989-E-01
4
2015/4