AK2400 Datasheet, PDF (39/52 Pages) Asahi Kasei Microsystems – High integrated receiver for PMR-LMR

[AK2400]
Typical Evaluation Board Schematic (PLL SYNTH)
AK2400
100pF
REFIN
CP
220nF
VREF1
Loop Filter
C1 ^R2'
R2
R3
C3
RFOUT
VCO
18Ω
100pF 18Ω
18Ω
SWIN
C2
CPZ
BIAS3 _RFINP
100pF
100pF
27kΩ _{３３３ RFINN}
51Ω
Figure 17 Typical Evaluation Board Schematic (PLL SYNTH)
[CPZ] pin should be connected to R2 and C2, which are intermediate nodes, even if the Fast Lockup feature
is not used. For the output destination from [CPZ] pin, see “Charge Pump and Loop Filter” on page 36.
R2 and R2’ are connected in parallel with internal switch in Fast Lockup. These R2 and R2’ parallel
resistance value is required for calculating loop bandwidth and phase margin in Fast Lockup. The
on-resistance value of the internal switch is 150Ω for reference.
1. PVDD, CPVDD
PVDD
100pF
0.01F
CPVDD
100pF
0.01F
10F
10F
LSI
Figure 18 PVDD, CPVDD
014008989-E-01
39
2015/4