AK2400 Datasheet, PDF (21/52 Pages) Asahi Kasei Microsystems – High integrated receiver for PMR-LMR

[AK2400]
Register Map and Function Description
Name
Address
D17
NUM
0x01
Initial Value
NUM
[17]
0
INT
0x02
CP1
[2]
Initial value 0
DIV
0x03
0
Initial value 0
CP_FAST ^0x04
0
Initial value 0
NSQ
0x05
VTSEL
[1]
Initial value 0
D16
NUM
[16]
0
CP1
[1]
0
INTE
0
FAST
EN
0
VTSEL
[0]
0
D15
NUM
[15]
0
CP1
[0]
0
CP
HiZ
0
CP2
[2]
0
0
0
D14
NUM
[14]
0
INT
[14]
0
DITH
0
CP2
[1]
0
D13
D12
NUM
[13]
0
NUM
[12]
0
INT
INT
[13]
[12]
0
0
LDCKSEL[ LDCKSEL[
1]
0]
0
0
CP2
FAST
[0]
[12]
0
1
D11
NUM
[11]
0
INT
[11]
0
LD
0
FAST
[11]
0
0
0
0
0
0
0
0
0
D10
NUM
[10]
0
INT
[10]
0
CP
POLA
0
FAST
[10]
0
0
0
D9
NUM
[9]
0
INT
[9]
0
PRE
[1]
0
FAST
[9]
0
0
0
D8
NUM
[8]
0
INT
[8]
0
PRE
[0]
0
FAST
[8]
0
0
0
D7
NUM
[7]
0
INT
[7]
0
R1
[7]
1
FAST
[7]
0
0
0
D6
NUM
[6]
0
INT
[6]
0
R1
[6]
0
FAST
[6]
0
0
0
D5
NUM
[5]
0
INT
[5]
0
R1
[5]
0
FAST
[5]
0
0
0
D4
NUM
[4]
0
INT
[4]
0
R1
[4]
0
FAST
[4]
0
0
0
D3
NUM
[3]
0
INT
[3]
0
R1
[3]
0
FAST
[3]
0
0
0
D2
NUM
[2]
0
INT
[2]
0
R1
[2]
0
FAST
[2]
0
0
0
D1
NUM
[1]
0
INT
[1]
0
R1
[1]
0
FAST
[1]
0
0
0
D0
NUM
[0]
0
INT
[0]
0
R1
[0]
0
FAST
[0]
0
0
0
OFFSET ^0x06
OFST
[17]
Initial value 0
OFST
[16]
0
OFST
[15]
0
OFST
[14]
0
OFST
[13]
0
OFST
[12]
0
OFST
[11]
0
OFST
[10]
0
OFST
[9]
0
OFST
[8]
0
OFST
[7]
0
OFST
[6]
0
OFST
[5]
0
OFST
[4]
0
OFST
[3]
0
OFST
[2]
0
OFST
[1]
0
OFST
[0]
0
IFBPF
0x07 ^{AGC_KEE AGCLVL_ AGCLVL_ AGCLVL_ AGCLVL_ AGCLVL_ AGCLVL_}
P
H[2]
H[1]
H[0]
L[2]
L[1]
L[0]
Initial value 0
1
0
1
1
0
0
CAL
AGC_FAS AGC_
T
TIME[1]
AGC_
TIME[0]
AGC1_
STEP
0
1
0
0
1
AGC_
OFF
0
BPF_BW BPF_BW BPF_BW LOFREQ LOFREQ
[2]
[1]
[0]
[1]
[0]
0
0
0
0
1
PGA
0x08
PGA0_L PGA2_G PGA2_G PGA2_G PGA2_G PGA2_G PGA1_G PGA1_G PGA1_G PGA1_G PGA1_G PGA1_G
G
[4]
[3]
[2]
[1]
[0]
[5]
[4]
[3]
[2]
[1]
[0]
Initial value 0
0
0
0
0
0
0
0
0
0
0
1
PGA0_
[2]
0
PGA0
[1]
1
PGA0
[0]
1
IFOG
[2]
0
IFOG
[1]
0
IFOG
[0]
1
0x09
0
SRST
0
0
0
0
0
0
0
0
SRST SRST SRST SRST SRST SRST SRST SRST
0
[7]
[6]
[5]
[4]
[3]
[2]
[1]
[0]
Initial value -
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
PD
0x0A
0
Initial value 0
RSSIMD
0
0
AGC_KEE SDATAOU
FMIX_IP3
P_SEL T_OE
DISLPF_G
[2]
DISLPF_G
[1]
DISLPF_G
[0]
FMIX_HV
PDTRI_N
BS[2]
BS[1]
BS[0]
PDSYNTH
_N
PDADC_N
PDFSTMI
X_N
BSSEL_F
MIX
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0x0B
PD_AGCG
Initial value
R_AGC1_ R_AGC1_ R_AGC1_ R_AGC1_ R_AGC1_ R_AGC1_ R_AGC2_ R_AGC2_ R_AGC2_ R_AGC2_ R_AGC2_
G[5]
G[4]
G[3]
G[2]
G[1]
G[0]
G[4]
G[3]
G[2]
G[1]
G[0]
-
-
-
-
-
-
-
-
-
-
-
Note1) Writing into address 0x01 is enabled when writing into address 0x02 is performed. Be sure to write into address 0x01 first and then address 0x02.
Note2) The initial register values are not defined. Therefore, even after [PDN] is set to “High”, each bit initial value remains undefined. In order to set all
register values, it is required to write the data in all addresses of the register.
Note3) Do not access the data except specified address 0x0c to 0x1F.
014008989-E-01
21
2015/4