AK2400 Datasheet, PDF (31/52 Pages) Asahi Kasei Microsystems – High integrated receiver for PMR-LMR

[AK2400]
Lock Detect function (PLL SYNTH)
In AK2400, “lock detect” output can be selected by D[11] = {LD} in <Address3>. When {LD} is set to “1”, the
phase frequency detector output provides a phase detection status as an analog level (comparison result).
This is called “Analog Lock Detect”. When {LD} is set to “0”, the lock detect signal outputs according to the
on-chip logic. This is called “Digital Lock Detect”.
Analog Lock Detect
In analog lock detect, the phase frequency detector output comes from the [LD] pin.
LD=1
Reference clock
PFD clock
VCO divide clock
Phase frequency
detector output
LD output
Figure 10 Analog Lock Detect
Digital Lock Detect
In the digital lock detect, the LD pin outputs ”Low” every time when the frequency is set. And the LD pin
outputs is “High” (which means the locked state) when a phase error smaller than T is detected for 63 times
consecutively. If the phase error is larger than T is detected for 63 times consecutively when the LD pin
outputs “High”, the LD pin outputs “Low”(which means the unlocked state).
The accuracy of the phase detect is set by LDCKSEL[1:0].
“00” : 1 cycle of the REFIN clock (This cannot be used for the reference dividing ratio ≤ 3.)
“01” : 2 cycle of the REFIN clock (This cannot be used for the reference dividing ratio ≤ 5.)
“10” : 3 cycle of the REFIN clock (This cannot be used for the reference dividing ratio ≤ 6.)
Since the AK2400 is a Delta-Sigma Fractional-N type, a phase error up to 7 times larger than the VCO
period frequency may occur in the phase frequency detector. Therefore the LDCKSEL[1:0] setting should
be large enough to cover the amplitude of the Delta-Sigma Fractional frequency. However, if the VCO
frequency does not satisfy either of the following formula, the digital lock detect cannot be used. In such
case, the analog lock detect should be used.
When {DITH} = D[14] in <Address3> is set to ”1” (DITH ON):
VCO frequency > [REFIN] pin input frequency / [LDCKSEL[1:0] setting + 1] × 7
When {DITH} = D[14] in <Address3> is set to “0” (DITH OFF):
VCO frequency > [REFIN] pin input frequency / [LDCKSEL[1:0] setting + 1] × 4
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