AK2400 Datasheet, PDF (11/52 Pages) Asahi Kasei Microsystems – High integrated receiver for PMR-LMR

[AK2400]
ADC AC Timing
At first, set {PDADC_N}=”1” to operate the A/D Converter. A/D conversion cycle is started by the falling
edge of AD_CSN. AD_SDO outputs “0” synchronized with the falling edge of AD_CSN. AD_SDO outputs “0”
until the third falling edge of AD_SCLK. From the fourth falling edge, the results of 12 bits A/D conversion
are output with MSB first during the 16th edge. A/D conversion cycle is ended on the 16th falling edge,
AD_SDO becomes Hi-Z. After the 16th edge, set AD_CSN =”1”. Since A/D converter becomes acquisition
phase after the 16th falling edge of AD_SCLK, AD_CSN pin must keep ”1” during the end of “tq” time after
AD_SDO became Hi-Z. It is possible to get the available conversion results from the next cycle, since the
first A/D conversion result is the dummy cycle (unavailable result).
D11 to D0 : A/D converted data
Figure 4 ADC Timing
Parameter
Symbol Conditions Min. Typ. Max. Unit
AD_SCLK frequency
fADSCLK
20
MHz
Minimum quiet time required between
Tq
bus relinquish and start of next
40
ns
conversion
AD_CSN Falling to First SCLK Falling
time
tCSS
10
ns
AD_CSN edge to AD_SDO Tri-State
Disabled
tDCD
25
ns
AD_SCLK Falling to AD_SDO Output
Delay time
tDOD 15pF load
25
ns
AD_SCLK High Pulse Width
tCKH
0.4×tA
DSCLK
ns
AD_SCLK Low Pulse Width
tCKL
0.4×tA
DSCLK
ns
16th AD_SCLK Falling to AD_SDO
Hi-Z State Delay time
tCCZ
25
ns
Minimum AD_CSN Pulse Width
tCSW
25
ns
Note) Digital input and output timing is relative to 0.5DVDD of rising signal and falling signal.
014008989-E-01
11
2015/4