AK4564 Datasheet, PDF (39/48 Pages) Asahi Kasei Microsystems – 16BIT CODEC WITH BUILT-IN ALC AND MIC/HP/SPK-AMP

ASAHI KASEI
[AK4564]
Timer Select
Addr
Register Name
06H ^{Timer Select}
Default
D7
TM1
0
D6
TM0
1
D5
D4
FDTM1 FDTM0
0
1
D3
ZTM1
1
D2
ZTM0
0
D1
WTM1
1
D0
WTM0
0
WTM1-0: ALC1 Recovery Waiting Period
A period of recovery operation when any limiter operation does not occur during ALC1 operation.
WTM1 WTM0 ALC1 Recovery Period
0
0
6ms
0
1
24ms
1
0
48ms
1
1
96ms
Table 14. ALC1 Recovery Operation Waiting Period
Default
ZTM1-0: IVOL Zero crossing Timeout Period
When IVOL of each L/R channels do zero crossing or timeout independently, the IVOL value is changed
by µP WRITE operation or ALC1 recovery operation.
ZTM1
ZTM0 Zero Crossing Timeout Period
0
0
6ms
0
1
24ms
1
0
48ms
Default
1
1
96ms
Table 15. Zero Crossing Timeout Period
FDTM1-0: FADEIN/OUT Cycle Setting
The FADEIN/OUT operation is done by a period set by FDTM1-0 bits when FDIN or FDOUT bits are set
to “1”. When IVOL of each L/R channel do zero crossing or timeout independently, the IVOL value is
changed.
FDTM1 FDTM0
FADEIN/OUT Period
0
0
20ms
0
1
40ms
1
0
48ms
1
1
56ms
Table 16. FADEIN/OUT Period
Default
TM1-0: Select zero crossing timeout period of OATT
These bits are enabled at ZCE = “1”.
TM1 TM0 Zero Crossing Timeout Period
0
0
8ms
0
1
16ms
1
0
32ms
1
1
64ms
Table 17. Select zero crossing timeout of OATT
Default
* WTM1-0, ZTM1-0, FDTM1-0 and TM1-0 have the same time between fs=32kHz (FSTM bit = “1”)
and fs=48kHz (FSTM bit = “0”).
MS0140-E-01
- 39 -
2002/07