AK4564 Datasheet, PDF (29/48 Pages) Asahi Kasei Microsystems – 16BIT CODEC WITH BUILT-IN ALC AND MIC/HP/SPK-AMP

ASAHI KASEI
[AK4564]
n FADEIN Mode
In FADEIN Mode, the IVOL value increase gradually by the step set by FDATT1-0 bits when FDIN bit changes from “0”
to “1”. The FADEIN period is set by FSTM, REF7-0, FDATT1-0 and FDTM1-0 bits. The FADEIN operation is done by
the zero crossing detection. The operation stops when the IVOL value becomes the REF value or the limiter detection
level (LMTH). If the limiter operation is done during FADAIN period, the FADEIN operation stops and the ALC1
operation starts.
NOTE: When FDIN and FDOUT bits are set to “1” at the same time, FADEOUT operation is prior to FADEIN operation.
SDTO Output
ALC1 bit
FDIN bit
(5)
(1) (2)
(3)
(4)
Figure 23. Example for controlling sequence in FADEIN operation
(1) WR (ALC1 = FDIN = “0”): The ALC1 operation is disabled. To start the FADEIN operation, FDIN bit is written in
“0”.
(2) WR (IVOL = “00H”): IVOL output is muted. The writing to IVOL should wait a zero crossing timeout
period set by ZTM1-0 bits.
(3) WR (ALC1 = FDIN = “1”): The FADEIN operation starts. The IVOL is fade-in from MUTE state.
(4) The FADEIN operation is done until the limiter detection level (LMTH1-0) or the reference level (REF7-0). After
completing the FADEIN operation. The FADEIN operation is completed and the ALC1 operation starts.
(5) FADEIN time is set by REF7-0, FDTM1-0, FSTM and FDATT bits
e.g. REF7-0 = E1H(225 dec), FDTM1-0 = 40ms, FDATT1-0 = 2 step
(225 x FDTM1-0) / FDATT1-0 = 225 x 40ms /2 = 4.5s
MS0140-E-01
- 29 -
2002/07