AK4564 Datasheet, PDF (34/48 Pages) Asahi Kasei Microsystems – 16BIT CODEC WITH BUILT-IN ALC AND MIC/HP/SPK-AMP

ASAHI KASEI
[AK4564]
Power Management Control
Addr
Register Name
D7
D6
D5
D4
D3
D2
D1
D0
02H Power Management Control AOUT2P AOUT1P SPKP HPP VCOM DAC ADC MIC
Default
1
1
1
0
1
1
1
1
MIC: MIC Block (Pre-Amp and MPWR) Power Control.
0: OFF
1: ON (Default)
When MIC bit = “0”, Output of Pre-Amp is Hi-Z and MPWR is terminated by 5kΩ (typ) to
MVSS.
ADC: ADC Power Control
0: OFF
1: ON (Default)
When ADC bit = “0”, SDTO pin is fixed to “L”. When ADC bit changes from “0” to “1”,
initializing cycle (4128/fs=86ms@fs=48kHz) starts. After initializing cycle, digital data of ADC
is generated.
DAC: DAC Power Control
0: OFF
1: ON (Default)
VCOM: Common Voltage (VCOM and HVCM) Power Control
0: OFF
1: ON (Default)
HPP: Headphone-Amp Power Control
0: OFF (Default)
1: ON
When HPP bit = “0”, output of Headphone-Amp becomes “L” (AVSS).
SPKP: Speaker Block Power Control (Including BEEP2, MOUT, ALC2 and Speaker-Amp)
0: OFF
1: ON (Default)
When SPKP bit = “0”, output of Speaker-Amp and MOUT are Hi-Z.
AOUT1P: LOUT1/ROUT1’s Amplifiers Power Control
0: OFF
1: ON (Default)
When AOUT1P bit = “0”, LOUT1/ROUT1 pins are Hi-Z.
AOUT2P: LOUT2/ROUT2’s Amplifiers Power Control
0: OFF
1: ON (Default)
When AOUT2P bit = “0”, LOUT2/ROUT2 pins are Hi-Z.
Each block can be partially powered-down by ON/OFF (“1” / “0”) of these bits. When PDN pin
goes “L”, all circuits are powered-down regardless of these bits. However in this case, all register
are reset to the default value.
When all these registers in 02H goes “0”, all circuits can be powered-down with keeping registers
values.
VCOM bit must go “1” before each block operates.
Except the case of MIC=ADC=DAC=VCOM=HPP=SPKP=AOUT1P=AOUT2P = “0” or PDN
pin = “L”, MCLK, BCLK and LRCK should not be stopped.
MS0140-E-01
- 34 -
2002/07