AK4564 Datasheet, PDF (11/48 Pages) Asahi Kasei Microsystems – 16BIT CODEC WITH BUILT-IN ALC AND MIC/HP/SPK-AMP

ASAHI KASEI
DC CHARACTERISTICS
(Ta=25°C; AVDD, DVDD, SVDD=2.6 ∼ 3.6V, MVDD, HVDD=2.6∼ 5.5V)
Parameter
Symbol
min
typ
High-Level Input Voltage
VIH
1.5
-
Low-Level Input Voltage
VIL
-
-
High-Level Output Voltage Iout=-200µA
VOH DVDD-0.2
-
Low-Level Output Voltage Iout=200µA
VOL
-
-
Input Leakage Current
Iin
-
-
SWITCHING CHRACTERISTICS
(Ta=25°C; AVDD, DVDD, SVDD=2.6 ∼ 3.6V, MVDD, HVDD=2.6∼ 5.5V; C_L=20pF)
Parameter
Symbol
min
typ
Master Clock Timing (MCLK)
256fs: Frequency
fCLK
2.048
12.288
Pulse Width Low
tCLKL
28
Pulse Width High
tCLKH
28
384fs: Frequency
fCLK
3.072
18.432
Pulse Width Low
tCLKL
23
Pulse Width High
tCLKH
23
LRCK Timing
Frequency
fs
8
48
Duty Cycle
Duty
45
50
Audio Interface Timing
BCLK Period
tBLK
312.5
BCLK Pulse Width Low
tBLKL
130
Pulse Width High
LRCK Edge to BCLK “↑” (Note 31)
BCLK “↑” to LRCK Edge (Note 31)
tBLKH
130
tLRB
50
tBLR
50
LRCK to SDTO (MSB) Delay Time
tLRM
BCLK “↓” to SDTO Delay Time
tBSD
SDTI Latch Hold Time
tSDH
50
SDTI Latch Set up Time
tSDS
50
Control Interface Timing
CCLK Period
tCCK
200
CCLK Pulse Width Low
tCCKL
80
Pulse Width High
tCCKH
80
CDTI Latch Set up Time
tCDS
50
CDTI Latch Hold Time
tCDH
50
CSN “H” Time
tCSW
150
CSN “↓” to CCLK “↑”
CCLK “↑” to CSN “↑”
tCSS
50
tCSH
50
Reset Timing
PDN Pulse Width
PDN “↑” to SDTO Delay Time
tPDW
150
tPDV
4128
Note 31. BCLK rising edge must not occur at the same time as LRCK edge.
[AK4564]
max
Units
-
V
0.6
V
-
V
0.2
V
±10
µA
max
Units
12.8
MHz
ns
ns
19.2
MHz
ns
ns
50
kHz
55
%
ns
ns
ns
ns
ns
80
ns
80
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1/fs
MS0140-E-01
- 11 -
2002/07