AK4564 Datasheet, PDF (24/48 Pages) Asahi Kasei Microsystems – 16BIT CODEC WITH BUILT-IN ALC AND MIC/HP/SPK-AMP

ASAHI KASEI
[AK4564]
n SPEAKER BLOCK
The output signal from DAC is converted into a mono signal, [(L+R)/2], and is supplied to Speaker-Amp via ALC2
circuit. This Speaker-Amp has a monaural output by BTL, which can be output up to 80mW at 8Ω. Speaker Blocks
(MOUT, ALC2 and Speaker-Amp) can be powered-up/down by SPKP bit. When SPKP bit is “0”, MOUT, SP0 and SP1
pins go Hi-Z. When SPPS bit is “0” and SPKP bit is “1”, Speaker-Amp becomes Power-Save-Mode. Then SP0 pin goes
Hi-Z and SP1 pin is output to SVDD/2 via 100k Ω (typ.).
When PDN pin changes from “L” to “H” after power-up, Speaker-Amp goes to Power-Save-Mode. In Power-Save-Mode,
SP1 pin gradually become HVCM voltage via an internal resistor (typ.200kΩ) from Hi-Z to decrease a pop noise. When
Power-down (SPKP = “0”), the pop noise can be decreased by controlling via Power-Save-Mode.
* When Headphone-Amp and Speaker-Amp are powered-up at the same time, refer to the condition of
“Note 7”, “Note 8” and “Note 10”.
1. Mono Output
MOUT pin outputs analog mixed signal, [(L+R)/2] of DAC output. When MOUT bit is “0”, this output is disabled and
MOUT pin goes to VCOM voltage. The load impedance is 10kΩ (min.). When SPKP bit is “0”, MOUT pin becomes
Power-Down-Mode and outputs Hi-Z.
2. ALC2
The input resistance of ALC2 is 23kΩ (typ.) and centered around VCOM voltage. The level diagram of ALC2
operation is shown in Figure 19
ALC2 limiter detection level is –6.5dBV regardless of power supply voltage. When the input signal level exceeds
–6.5dBV (=FS-2dB@AVDD=2.8V), the output level of ALC2 is limited.
When the signal over –6.5dBV and is input continuously to the ALC2 circuit, the changing period of ALC2 limiter
operation is 2/fs=42µs@fs=48kHz and the output level is attenuated by 0.5dB/step. The ALC2 recovery operation is
done by zero crossing detection and the output is gained by 1dB/step. The ALC2 recovery operation is done until the
output level of Speaker-Amp goes to –8.5dBV(=FS-4dB@AVDD=2.8V). The ALC2 recovery operation period is fixed
to 2048/fs=42.7mS@fs=48kHz. When inputting signal between –6.5dBV and –8.5dBV, both the limiter and recovery
operations of ALC2 are not done.
When PDN pin changes from “L” to “H” or SPKP bit changes from “0” to “1”, the initilizing cycle (2048/fs = 42.7ms
@fs=48kHz) starts. ALC2 is disabled during initilizing cycle, ALC2 starts after finishing the initilizing cycle.
Parameter
Operation Start Level
Period
fs=48kHz
fs=32kHz
Zero Crossing Detection
ATT/GAIN
ALC2 Limiter operation
-6.5dBV
2/fs = 42µs
2/fs = 63µs
No
0.5dB step
Table 4. Content of ALC2
ALC2 Recovery operation
-8.5dBV
2048/fs = 42.7ms
2048/fs = 64ms
Yes(Timeout = 2048/fs )
1dB step
MS0140-E-01
- 24 -
2002/07