AK8998 Datasheet, PDF (38/59 Pages) Asahi Kasei Microsystems – Preliminary

3) Flow chart of Digital block
The flow chart of digital block is shown below.
The flow chart of digital block
POWER ON
Normal Mode
VOUT
: Analog Output
No _{CSCLK=”High” Yes}
> 1.0 ms
Timing chart1
EEPROM Write
Instruction code
: 101
EEPROM Read
Instruction code
: 110
Digital I/O Mode
VOUT
: DATA I/O
Register Read
Instruction code
: 010
[AK8998/W/D]
note1)
In DATA I/O mode, when the condition of CSCLK=Low > 0.5 ms consists,
it becomes an Analog Output mode.
note2)
The state of EEPROM Write Enable and Control Register Access Enable
is required.
Register Write
Instruction code
: 001
CSCLK=”High”
(Write Time)
> 5ms
Timing chart2
VREF
Adjustment set
VTMP
Adjustment set
IREF
Adjustment set
S/H err
Adjustment set
Pressure Detector 1/2 Pressure Detector 1/2
Threshold
Hysteresis Level
Adjustment set
Adjustment set
Timing chart3
OSC
Adjustment set
Between
CSCLK="High"
VOUT : VREF
Between
CSCLK="High"
VOUT : VTMP
Between
CSCLK="High"
VOUT : IREF
Between
CSCLK="High"
VOUT : S/H Out
Between
CSCLK="High"
VOUT
: Pressure Level
Between
CSCLK="High"
VOUT : Pressure
Hysteresis Level
Between
CSCLK="High"
OSC clock counting
CSCLK=”Low”
No
> 0.5 ms
Yes
CSCLK=”Low”
> 0.5 ms
No
Yes
MSxxxxx-E-00
- 37 -
2012/11