AK8998 Datasheet, PDF (27/59 Pages) Asahi Kasei Microsystems – Preliminary

[AK8998/W/D]
Functional Description
1) Adjustment Procedure Description (Example)
The adjustment procedure for the AK8998 follows (See "Adjustment Sequence.").
Note) When shipped in package form, the adjustments for the items 1-4 below have been
completed. It is necessary to read the data (items 1-4 below) from a chip first and after initializing
the EEPROM, rewrite the readout data. Note that depending on the required accuracy and
implementation form, there could be some cases where items 1-4 should be readjusted.
AK8998 is shipped with adjustment at VDD=5V & VS=4V mode (EVD[1:0]=0h) and internal
temperature sensor use (ETMP[0]=1h). If other modes (EVD[1:0]=1, 2, 3h, ETMP[0]=0h) are the
actual operating condition, readjustment is required. Even if VDD=5V&VS=4V (EVD[1:0]=0h)
and internal temperature sensor use (ETMP[0]=1h) are the operating condition, readjustment
is recommended.
Keep the sequence as adjustment of VREF adjustment, IREF adjustment, OSC adjustment, and
VTMP adjustment in turn. If VREF adjustment and IREF adjustment are performed after OSC
adjustment, adjusted Oscillating frequency will shift.
The EEPROM address is referred to as "address," while the control register (volatile memory)
address is referred to as "C address."
1. VREF Adjustment (completed when shipped in package form)
The reference voltage is adjusted to 1.0V by VREF voltage adjustment EEPROM (address: 0Eh,
data EVR[2:0]). Adjusting the VREF voltage also means adjustment of the sensor drive voltage
(VS). VREF voltage is observed at VOUT pin (See “Recommended Connection Examples for
Components”) while the CSCLK pin High (CSCLK High Time) after the writing of an adjustment
mode register (C address: 00h, data AM[3:0]= 1h).
Twr_REG CSCLK High Time
1
4
9
16
1
CSCLK
VOUT
Analog
Output
Hi-z
VREF monitor
I2
2. IREF Adjustment (completed when shipped in package form)
The reference current is adjusted to 1.0µA.
The external resistor (1MΩ) is connected to VOUT pin. Reference current is supplied to the
external resistor, and IREF current adjustment EEPROM (address: 0Fh, data EIR[3:0]) is adjusted
so that the voltage across the both ends of the external resistor is set to 1.0V. And it can adjust
more accurate by taking into consideration the input impedance (input resistance) of adjustment
apparatus. With 1MΩ external resistor to the VOUT pin, it is adjusted in voltage domain. The
external 1MΩ should be connected only at the time of IREF adjustment. When with resistance
1MΩ is connected always in outside, please be careful of the input impedance of adjustment
apparatus. The input impedance of adjustment apparatus should become more than 10GΩ. IREF
current is observed at VOUT pin (See “Recommended Connection Examples for Components”)
while the CSCLK pin High (CSCLK High Time) after the writing of an adjustment mode register (C
address: 00h, data AM[3:0]= 2h).
Twr_REG CSCLK High Time
1
4
CSCLK
VOUT
Analog
Output
MSxxxxx-E-00
9
- 26 -
16
Hi-z
1
IREF monitor
I2
2012/11