AK8998 Datasheet, PDF (32/59 Pages) Asahi Kasei Microsystems – Preliminary

[AK8998/W/D]
14. Output Span Voltage Fine Adjustment
The output span voltage error is caused by compensating the offset voltage temperature drift. The
output span voltage is adjusted using the output span voltage adjustment register (Address: 02h
data: ESC[7:0]).
2) Finding the VOUT and VO Pins External Capacitance (Cap)
This section explains how the VOUT and VO pins external capacitance is defined.
The requirements for determining the VOUT and VO pins external capacitance values are the
stabilization time on power-up and S/(N+D)=Signal/(Noise+Distortion).
1. VOUT Pin Output Voltage Stabilization Time
Note that depending on the VOUT and VO pins external capacitance values, the measurement
values (VOUT pin voltage) may contain errors upon power-up.
"99% Settling time ( + in the figure)" in the table below represents the analog stabilization time
in the figure and the time required to settle down to 99% of the output voltage (0.1*VDD in this case)
according to the pressure applied during the period ( + in the figure).
The period in the figure is 0.30msec (typ).
Subsequently, the output voltage will settle to 99% according to the pressure during period in the
figure. When the VO pin capacitance is 1µF, the period in the figure will settle within 672.4msec.
Settling time (period in the figure) =-146[kΩ]*1[µF]*ln(1-99/100)=672.4 [msec]
Therefore, the settling time up to 99% (period + in the figure) will be as follows:
99% settling time (period + in the figure) = 0.30[msec] + 672.4[msec] = 672.7 [msec]
Referring to the previous calculation example, determine the stabilization time based on true terms
of use:
Prerequisites: VO pin external capacitance:
VO pin internal resistance:
Period in the figure:
Cap（Cap[µF] typ., Cap*1.1[µF] worst）
Res（146[kΩ] typ., 190[kΩ] worst）
Time（0.30[msec] typ., 0.40[msec] worst）
Settling time (period in the figure) = -Res*Cap*In(1-99/100)
99% settling time (period + in the figure) = Time + Settling time
VDD pin voltage
Sample timing
e.g. When sampling frequency is 10kHz and VOUT/VO
pin capacitance is 1µF.
VO&VOUT pin voltage
Hi-Z
- Reference designators
: Sampling timing; this diagram represents 10kHz (0.1msec).
: Power-up rise time (VDD).
: Settling time for stable analog operation.
: Pressure signal detection time. This time depends on the VO pin external capacitance and the internal 146kΩ
resistance.
MSxxxxx-E-00
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2012/11