AK4342 Datasheet, PDF (36/43 Pages) Asahi Kasei Microsystems – 24-Bit Stereo DAC with HP-AMP & 2V Line-Out

ASAHI KASEI
[AK4342]
Addr
03H
Register Name
Mode Control 2
R/W
Default
D7
D6
D5
D4
D3
D2
D1
D0
PGAC PTS1 PTS0 STS1 STS0 DATTC BCKP LRP
R/W R/W R/W R/W R/W R/W R/W R/W
0
0
0
0
1
0
0
0
LRP: LRCK Polarity Select
0: Normal (Default)
1: Invert
BCKP: BICK Polarity Select
0: Normal (Default)
1: Invert
DATTC: DAC Digital Attenuator Control Mode Select
0: Independent (Default)
1: Dependent
At DATTC bit = “1”, ATTL7-0 bits control both Lch and Rch attenuation level, while register values of
ATTL7-0 bits are not written to ATTR7-0 bits. At DATTC bit = “0”, ATTL7-0 bits control Lch level and
ATTR7-0 bits control Rch level.
STS1-0: Soft mute cycle setting (See Table 7)
Default: “01” (1020LRCK at Normal Speed Mode)
PTS1-0: Select Transition time for AMUTE, LINL, LINR, RINL, RINR, DACLR, LPGA4-0, PGAL4-0,
PGAR4-0, LMUTE, HMUTEL and HMUTER (See Table 15)
Default: “00”
PGAC: PGA Control Mode Select
0: Independent (Default)
1: Dependent
At PGAC bit = “1”, PGL4-0 bits control both Lch and Rch attenuation level, while register values of
PGAL4-0 bits are not written to PGAR4-0 bits. At PGAC bit = “0”, PGAL4-0 bits control Lch level and
PGAR4-0 bits control Rch level.
Addr
04H
05H
Register Name
Lch PGA Control
Rch PGA Control
R/W
Default
D7
D6
D5
D4
D3
D2
D1
D0
0
0 HMUTEL PGAL4 PGAL3 PGAL2 PGAL1 PGAL0
0
0 HMUTER PGAR4 PGAR3 PGAR2 PGAR1 PGAR0
RD
RD
R/W R/W R/W R/W R/W R/W
0
0
1
1
1
0
0
1
PGAL4-0: Setting of analog volume for Lch (See Table 10)
HMUTEL: Mute control for HPL
0: Normal operation
PGAL4-0 bits control attenuation value.
1: Mute. (Default)
PGAL4-0 bits are ignored.
PGAR4-0: Setting of analog volume for Rch (See Table 10)
HMUTER: Mute control for HPR
0: Normal operation
PGAR4-0 bits control attenuation value.
1: Mute. (Default)
PGAR4-0 bits are ignored.
MS0506-E-02
- 36 -
2006/07